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1. 发明授权

US07320022B2 System on a chip for caching of data packets based on a cache miss/hit and a state of a control signal 有权
标题翻译：基于高速缓存未命中/缓存和控制信号的状态来缓存数据分组的芯片上的系统
公开(公告)号：US07320022B2
公开(公告)日：2008-01-15
申请号：US10202753
申请日：2002-07-25
申请人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
发明人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
IPC分类号： G06F13/00
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042
摘要： A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
摘要翻译：分组处理系统可以包括集成到单个集成电路中的处理器，高速缓存，存储器控制器和至少一个分组接口电路。在一个实施例中（其可以在集成或非集成系统中使用），分组接口电路被配置为在接收到的分组的一部分的高速缓存中引起分配。在一个实施例中（其可以在集成或非集成系统中使用），存储器控制器可以被配置为选择性地阻止存储器事务。特别地，存储器控制器可以实现至少两个块信号，一个用于分组接口电路，一个用于其他设备。当存储器控制器的输入队列逼近时，块信号可用于控制存储器事务的启动。

2. 发明授权

US07287649B2 System on a chip for packet processing 失效
标题翻译：系统在芯片上进行数据包处理
公开(公告)号：US07287649B2
公开(公告)日：2007-10-30
申请号：US09861188
申请日：2001-05-18
申请人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
发明人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
IPC分类号： G06F13/00
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042
摘要： A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
摘要翻译：分组处理系统可以包括集成到单个集成电路中的处理器，高速缓存，存储器控制器和至少一个分组接口电路。在一个实施例中（其可以在集成或非集成系统中使用），分组接口电路被配置为在接收到的分组的一部分的高速缓存中引起分配。在一个实施例中（其可以在集成或非集成系统中使用），存储器控制器可以被配置为选择性地阻止存储器事务。特别地，存储器控制器可以实现至少两个块信号，一个用于分组接口电路，一个用于其他设备。当存储器控制器的输入队列逼近时，块信号可用于控制存储器事务的启动。

3. 发明授权

US06851004B2 Adaptive retry mechanism 有权
标题翻译：自适应重试机制
公开(公告)号：US06851004B2
公开(公告)日：2005-02-01
申请号：US10629097
申请日：2003-07-29
申请人： James B. Keller , Chun H. Ning , Kwong-Tak A. Chui , Mark D. Hayter
发明人： James B. Keller , Chun H. Ning , Kwong-Tak A. Chui , Mark D. Hayter
IPC分类号： G06F13/00 , G06F13/14 , G06F13/16 , G06F13/36
CPC分类号： G06F13/161
摘要： An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected. On the other hand, if latencies greater than the maximum retry latency are being experienced, the minimum retry latency may be selected.
摘要翻译：自适应重试机制可以记录近期事务的延迟（例如，第一数据传输等待时间），并且可以从两个或更多个重试延迟中选择重试延迟。重试延迟可以用于事务，并且可以在事务中指定在第一数据传送尚未发生的情况下重试事务的时间点。在一个实现中，该重试延迟集合包括最小重试延迟，标称重试延迟和最大重试延迟。标称重试延迟可以被设置为略大于系统中事务的预期等待时间。最小重试延迟可能小于标称重试延迟，并且最大重试延迟可能大于标称重试延迟。如果正在经历大于标称重试延迟但小于最大重试延迟的延迟，则可以选择最大重试延迟。另一方面，如果正在经历大于最大重试延迟的延迟，则可以选择最小重试延迟。

4. 发明授权

US06633936B1 Adaptive retry mechanism 有权
标题翻译：自适应重试机制
公开(公告)号：US06633936B1
公开(公告)日：2003-10-14
申请号：US09670362
申请日：2000-09-26
申请人： James B. Keller , Chun H. Ning , Kwong-Tak A. Chui , Mark D. Hayter
发明人： James B. Keller , Chun H. Ning , Kwong-Tak A. Chui , Mark D. Hayter
IPC分类号： G06F1300
CPC分类号： G06F13/161
摘要： An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected. On the other hand, if latencies greater than the maximum retry latency are being experienced, the minimum retry latency may be selected.
摘要翻译：自适应重试机制可以记录近期事务的延迟（例如，第一数据传输等待时间），并且可以从两个或更多个重试延迟中选择重试延迟。重试延迟可以用于事务，并且可以在事务中指定在第一数据传送尚未发生的情况下重试事务的时间点。在一个实现中，该重试延迟集合包括最小重试延迟，标称重试延迟和最大重试延迟。标称重试延迟可以被设置为略大于系统中事务的预期等待时间。最小重试延迟可能小于标称重试延迟，并且最大重试延迟可能大于标称重试延迟。如果正在经历大于标称重试延迟但小于最大重试延迟的延迟，则可以选择最大重试延迟。另一方面，如果正在经历大于最大重试延迟的延迟，则可以选择最小重试延迟。

5. 发明授权

US07003615B2 Tracking a non-posted writes in a system using a storage location to store a write response indicator when the non-posted write has reached a target device 有权
标题翻译：当非发布的写入已到达目标设备时，使用存储位置跟踪系统中的未发布的写入以存储写入响应指示符
公开(公告)号：US07003615B2
公开(公告)日：2006-02-21
申请号：US10127130
申请日：2002-04-22
申请人： Kwong-Tak A. Chui , Shun Wai Go , Mark D. Hayter , Chun H. Ning , Amy K. Silveria
发明人： Kwong-Tak A. Chui , Shun Wai Go , Mark D. Hayter , Chun H. Ning , Amy K. Silveria
IPC分类号： G06F13/36
CPC分类号： G06F13/4217
摘要： An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.
摘要翻译：一种装置包括存储位置和耦合到存储位置的写监视器电路。存储位置被配置为存储能够指示接收至少一个写入响应的写入响应指示符。每个写入响应指示相应的写入已到达该写入的目标器件。写入监视器电路被配置为响应于接收到第一写入响应的指示来更新写入响应指示符。计算机可访问介质可以包括指令，当被执行时：（i）初始化写入响应指示符; 以及（ii）向目标设备发出一个或多个写入，其中所述目标设备被配置为响应于由所述写入响应指示符指示的写入响应。

6. 发明申请

US20100188980A1 Explicit Flow Control in a Gigabit/10 Gigabit Ethernet System 审中-公开
标题翻译：千兆/万兆以太网系统中的显式流量控制
公开(公告)号：US20100188980A1
公开(公告)日：2010-07-29
申请号：US12753466
申请日：2010-04-02
申请人： Shailendra S. Desai , Mark D. Hayter
发明人： Shailendra S. Desai , Mark D. Hayter
IPC分类号： H04L1/00
CPC分类号： H04L47/245 , H04L47/10 , H04L47/13
摘要： In one embodiment, a system comprises a communication medium; a first controller coupled to the communication medium; and a second controller coupled to the communication medium. The first controller is configured to interrupt transmission of a packet on the communication medium to the second controller subsequent to transmission of a first portion of the packet. The first controller is configured to transmit at least one control symbol on the communication medium in response to interrupting transmission of the packet, and wherein the first controller is configured to continue transmission of the packet with a second portion of the packet. The controller(s) may include, in some embodiments, a media access controller and a physical coding sublayer.
摘要翻译：在一个实施例中，系统包括通信介质; 耦合到所述通信介质的第一控制器; 以及耦合到所述通信介质的第二控制器。第一控制器被配置为在传送分组的第一部分之后中断在通信介质上的分组到第二控制器的传输。第一控制器被配置为响应于中断分组的传输而在通信介质上发送至少一个控制符号，并且其中第一控制器被配置为继续使用分组的第二部分传输分组。在一些实施例中，控制器可以包括媒体访问控制器和物理编码子层。

7. 发明授权

US07836220B2 Network direct memory access 有权
标题翻译：网络直接内存访问
公开(公告)号：US07836220B2
公开(公告)日：2010-11-16
申请号：US11505736
申请日：2006-08-17
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： G06F13/28 , G06F15/16 , G06F15/167
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为执行与本地存储器的一次或多次传输，以响应于第一分组访问由第一分组指定的数据从数据链路层接收。第二个节点被配置为将另一个分组处理到协议栈的顶部。

8. 发明授权

US08495257B2 Network direct memory access 有权
标题翻译：网络直接内存访问
公开(公告)号：US08495257B2
公开(公告)日：2013-07-23
申请号：US12908741
申请日：2010-10-20
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为响应于接收到的第一分组而与本地存储器执行多一次传输以访问由第一分组指定的数据从数据链路层。第二个节点被配置为将另一个分组处理到协议栈的顶部。

9. 发明申请

US20110035459A1 Network Direct Memory Access 有权
标题翻译：网络直接内存访问
公开(公告)号：US20110035459A1
公开(公告)日：2011-02-10
申请号：US12908741
申请日：2010-10-20
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： G06F15/167
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为执行与本地存储器的一次或多次传输，以响应于第一分组访问由第一分组指定的数据从数据链路层接收。第二个节点被配置为将另一个分组处理到协议栈的顶部。

10. 发明申请

US20080043732A1 Network direct memory access 有权
标题翻译：网络直接内存访问
公开(公告)号：US20080043732A1
公开(公告)日：2008-02-21
申请号：US11505736
申请日：2006-08-17
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： H04L12/56
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为执行与本地存储器的一次或多次传输，以响应于第一分组访问由第一分组指定的数据从数据链路层接收。第二个节点被配置为将另一个分组处理到协议栈的顶部。

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