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1. 发明授权

US6125444A Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all 失效
标题翻译：提供全球分支历史表的具有Millimode功能的计算机系统禁用和分离的millicode禁用，这使得可以关闭某些代码段但不对所有的代码执行millicode禁用
公开(公告)号：US6125444A
公开(公告)日：2000-09-26
申请号：US70201
申请日：1998-04-30
申请人： Mark Anthony Check , John Stephen Liptay , Timothy John Slegel , Charles Franklin Webb , Mark Steven Farrell
发明人： Mark Anthony Check , John Stephen Liptay , Timothy John Slegel , Charles Franklin Webb , Mark Steven Farrell
IPC分类号： G06F9/22 , G06F9/26 , G06F9/38
CPC分类号： G06F9/3844
摘要： A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.
摘要翻译：具有毫米级功能的计算机系统提供对millicode的控制以允许BHT操作继续，除非出现这些特殊情况需要提供指令提取操作的控制，并且BHT可以在某些代码执行部分被关闭但不被禁用对全部。单个免费运行的BHT功能可用于中央处理器的正常模式和毫模式，可以以毫米模式执行，其中分支历史表指示全局BHT禁用和毫代码禁用两者之间存在禁用指令的指令提取。命中检测逻辑接收来自全局BHT禁用的输入，以及从初始化的控制寄存器位和处理器控制寄存器位选择正确的设置目标信息并生成“检测到分支历史表命中”控制信号。

2. 发明授权

US6108776A Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer 失效
标题翻译：在毫秒支持计算机中的millicode例程的敏感部分，全局或选择性地禁用分支历史表操作
公开(公告)号：US6108776A
公开(公告)日：2000-08-22
申请号：US70362
申请日：1998-04-30
申请人： Mark Anthony Check , John Stephen Liptay , Timothy John Slegel , Charles Franklin Webb , Mark Steven Farrell
发明人： Mark Anthony Check , John Stephen Liptay , Timothy John Slegel , Charles Franklin Webb , Mark Steven Farrell
IPC分类号： G06F9/22 , G06F9/26 , G06F9/318 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3806 , G06F9/3017
摘要： A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.
摘要翻译：具有毫米级功能的计算机系统提供对millicode的控制以允许BHT操作继续，除非出现这些特殊情况需要提供指令提取操作的控制，并且BHT可以在某些代码执行部分被关闭但不被禁用对全部。单个免费运行的BHT功能可用于中央处理器的正常模式和毫模式，可以以毫米模式执行，其中分支历史表指示全局BHT禁用和毫代码禁用两者之间存在禁用指令的指令提取。命中检测逻辑接收来自全局BHT禁用的输入，以及从初始化的控制寄存器位和处理器控制寄存器位选择正确的设置目标信息并生成“检测到分支历史表命中”控制信号。

3. 发明授权

US6085313A Computer processor system for executing RXE format floating point instructions 失效
标题翻译：用于执行RXE格式浮点指令的计算机处理器系统
公开(公告)号：US6085313A
公开(公告)日：2000-07-04
申请号：US070198
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145
摘要： A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation. Instructions of the RX-type are extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine from the first 8 bits of the operation code alone, the exact format of the instruction. Instructions formats include the ESA/390 instructions SS, RR; RX; S; RRE; RI: and the new RXE instructions. where instructions of the RXE format have their R.sub.1, X.sub.2, B.sub.2, and D.sub.2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.RXE instructions can be used for floating point processing and fixed point processing.
摘要翻译：一种计算机处理器系统，具有用于指令的浮点处理器，其在六个周期流水线中被处理，其中在流水线的第一周期之前取出指令文本，并且在所读取的特定指令的第一周期期间对其进行解码，读取基地址（B）和索引（X）寄存器值以用于地址生成。通过将操作代码的扩展置于指令格式的前四个字节之外来扩展RX类型的指令，并且以这样的方式分配操作代码，使得机器可以仅从操作代码的前8位确定，指令的确切格式。指令格式包括ESA / 390指令SS，RR; RX; S; RRE; RI：和新的RXE指令。其中RXE格式的指令在RX格式中在所述指令寄存器中的相同位置具有它们的R1，X2，B2和D2字段，以使处理器仅从操作代码的前8位确定指令为解码的是RXE格式指令和RXE格式指令的寄存器索引扩展，然后将正确的信息写入所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所提取的指令结果放在第六个循环中.RXE指令可用于浮点处理和定点处理。

4. 发明授权

US6105126A Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code 失效
标题翻译：地址比特解码用于RXE指令格式的相同加法器电路，具有与RX格式相同的XBD位置和解码的扩展操作码
公开(公告)号：US6105126A
公开(公告)日：2000-08-15
申请号：US70359
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/34
CPC分类号： G06F9/355 , G06F9/30185
摘要： A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.
摘要翻译：计算机处理器浮点处理器六循环流水线系统，其中指令文本在第一周期之前获取并且在第一周期期间被解码用于所提取的特定指令，并且基准（B）和索引（X）寄存器值被读取用于地址代。 RXE指令是RX型，但通过将操作码的扩展置于指令格式的前四个字节之外进行扩展，并以这样的方式分配操作码，使得机器可以从前8位确定确切的格式的操作代码。 ESA / 390指令SS，RR; RX; S; RRE; RI; 并且新的RXE指令具有可用于固定点处理以及浮点处理的格式，其中RXE格式的指令在所述指令寄存器中的相同位置具有其R1，X2，B2和D2字段，如 RX格式，使处理器能够从操作代码的前8位确定正在解码的指令是RXE格式指令和RXE格式指令的寄存器索引扩展，之后它将正确信息锁定到所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所取出的指令结果放在第六个周期。

5. 发明授权

US6119219A System serialization with early release of individual processor 失效
标题翻译：系统串行化与早期发布的单个处理器
公开(公告)号：US6119219A
公开(公告)日：2000-09-12
申请号：US70595
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F15/177 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/52 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/30101 , G06F9/3017 , G06F9/3834
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

6. 发明授权

US06079013A Multiprocessor serialization with early release of processors 失效
标题翻译：多处理器串行化与早期版本的处理器
公开(公告)号：US06079013A
公开(公告)日：2000-06-20
申请号：US70429
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F9/52 , G06F9/318 , G06F12/06
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3017
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

7. 发明授权

US6105109A System speed loading of a writable cache code array 失效
标题翻译：可写缓存代码数组的系统速度加载
公开(公告)号：US6105109A
公开(公告)日：2000-08-15
申请号：US26327
申请日：1998-02-19
申请人： Barry Watson Krumm , Charles Franklin Webb , Timothy John Slegel , Mark Steven Farrell , Yuen Hung Chan
发明人： Barry Watson Krumm , Charles Franklin Webb , Timothy John Slegel , Mark Steven Farrell , Yuen Hung Chan
IPC分类号： G06F9/38 , G06F12/08 , G06F13/00 , G06F9/28
CPC分类号： G06F9/3802 , G06F12/0802
摘要： SMP computers systems can add to the first level cache a fill mode latch and achieve straightforward, high-performance loading of a writable cache code array that is part of a hierarchical cache structure.A new code array's write control elements include a control latch called "fill mode" for the BCE controls which when fill mode is active, then a disable is also active, since reads of the code array may not give accurate data when the array is not yet filled-up/fully valid. New mode follows the sequential steps which process code by:a) purge the cache array; thenb) disable the code array; thenc) turn on fill mode with a buffer control element fill mode latch; and then processd) code increments once through a range of line addresses, where the range is at least as wide as the range(s) specified in the code array's lookup mechanism.e) turn off fill mode; thenf) purge the cache array again: and theng) enable the code array (turn off the code array disable bit).h) resume normal operation to end the sequence.
摘要翻译： SMP计算机系统可以将第一级缓存添加到填充模式锁存器中，并实现作为分层缓存结构的一部分的可写缓存代码数组的直接，高性能加载。新的代码数组的写控制元素包括称为“ 填充模式“，当填充模式处于活动状态时，禁用也是活动的，因为当数组尚未填满/完全有效时，代码数组的读取可能无法提供准确的数据。新模式遵循以下步骤处理代码的顺序步骤：a）清除缓存数组; 那么b）禁用代码数组; 然后c）用缓冲器控制元件填充模式锁存器打开填充模式; 然后处理d）通过行地址范围增加一次代码，其范围至少与代码数组查找机制中指定的范围一样宽。 e）关闭填充模式; 然后f）再次清除缓存数组：然后g）启用代码数组（关闭代码数组禁用位）。 h）恢复正常操作以结束序列。

8. 发明授权

US6055624A Millicode flags with specialized update and branch instructions 失效
标题翻译：具有专门更新和分支指令的Millicode标志
公开(公告)号：US6055624A
公开(公告)日：2000-04-25
申请号：US56485
申请日：1998-04-07
申请人： Charles Franklin Webb , Mark Steven Farrell , Timothy John Slegel
发明人： Charles Franklin Webb , Mark Steven Farrell , Timothy John Slegel
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/318 , G06F9/32
CPC分类号： G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/3005 , G06F9/30094 , G06F9/3017
摘要： A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string. Translate Fetch (TRFET) millicode instructions support a Translate and Test TRT instruction and specialized millicode instructions for packed decimal division make use of the hardware control and dataflow logic designed to support simpler packed decimal operations including Add to provide operand access, checking, preparation, and storing functions, and to generate the quotient digits as needed for the DP instruction are implemented as as internal code instructions, rather than implementing the entire DP function in hardware, and control is maintained in internal code allowing simpler handling of unusual and boundary conditions.
摘要翻译：一种具有流水线计算机处理器的计算机系统，其在硬件控制执行单元中执行相对简单的指令集，并且在所述硬件控制的执行单元中以简单指令的毫位序列在毫模式架构状态下执行相对复杂的指令集，当所述处理器的宏模式解码被暂停以使得系统随后使用处理器毫秒寄存器并且处理器的解码器对它们进行解码并在进入处理器毫模式时进行调度以进行执行，以毫模式状态工作的毫代数。 Millicode标志允许专门的更新和分支指令和标志被清除或专门设置为一个millicode指令。用于编辑功能的millicode指令处理输入模式字符串的一个字节，生成输出字符串的一个字节，并更新各种指针和状态指示，以准备处理字符串中的下一个字节。 Translate Fetch（TRFET）millicode指令支持翻译和测试TRT指令和专门的millicode指令，用于打包十进制分割，使用硬件控制和数据流逻辑，用于支持更简单的打包十进制操作，包括添加以提供操作数访问，检查，准备和存储功能，并根据DP指令的需要生成商数字，作为内部代码指令而实现，而不是在硬件中实现整个DP功能，并且内部代码中的控制保持在更简单的处理异常和边界条件中。

9. 发明授权

US06178495B1 Processor E-unit to I-unit interface instruction modification with E-unit opcode computer logic in the unit 失效
标题翻译：处理器E单元到I单元接口指令修改，具有E单元操作码计算机逻辑单元
公开(公告)号：US06178495B1
公开(公告)日：2001-01-23
申请号：US09070537
申请日：1998-04-30
申请人： Timothy John Slegel , Mark Anthony Check
发明人： Timothy John Slegel , Mark Anthony Check
IPC分类号： G06F930
CPC分类号： G06F9/30181 , G06F9/30145 , G06F9/328 , G06F9/3861
摘要： A computer processor which has a apparatus in its Execution Unit (E-unit) that detects a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer provides a method for alleviating design deficiencies in the processor. The E-unit further contains a mechanism for transmitting the opcode and a desired action back to the Instruction Unit (I-unit) where it may be compared with the next instruction that is decoded. Furthermore, the E-unit opcode compare logic contains a mechanism for breaking infinite loops that may result. This E-unit opcode compare mechanism, may also be used for other purposes such as detecting invalid opcodes and other exception checking since it may allow for a faster cycle time of the processor than if this logic were implemented in the I-unit.
摘要翻译：在其执行单元（E单元）中具有检测待执行的操作码与计算机制造商编程的操作码之间的匹配的计算机处理器提供了一种减轻处理器中的设计缺陷的方法。 E单元还包含用于将操作码和期望动作发送回指令单元（I单元）的机制，在该单元中可以将其与下一个被解码的指令进行比较。此外，E单元操作码比较逻辑包含用于打破可能导致的无限循环的机制。该E单元操作码比较机制也可用于其他目的，例如检测无效操作码和其他异常检查，因为与I单元中实现的逻辑相比，它可能允许处理器的周期更快。

10. 发明授权

US6092185A Opcode compare logic in E-unit for breaking infinite loops, detecting invalid opcodes and other exception checking 失效
标题翻译：用于打破无限循环的E单元中的操作码比较逻辑，检测无效操作码和其他异常检查
公开(公告)号：US6092185A
公开(公告)日：2000-07-18
申请号：US70538
申请日：1998-04-30
申请人： Timothy John Slegel , Mark Anthony Check
发明人： Timothy John Slegel , Mark Anthony Check
IPC分类号： G06F9/30 , G06F9/318 , G06F11/36 , G06F9/312 , G06F9/48
CPC分类号： G06F9/30145 , G06F11/3648 , G06F9/30181 , G06F9/3861
摘要： A computer processor which has an apparatus in its Execution Unit (E-unit) that detects a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer provides a method for alleviating design deficiencies in the processor. The E-unit further contains a mechanism for transmitting the opcode and a desired action back to the Instruction Unit (I-unit) where it may be compared with the next instruction that is decoded. Furthermore, the E-unit opcode compare logic contains a mechanism for breaking infinite loops that may result. This E-unit opcode compare mechanism, may also be used for other purposes such as detecting invalid opcodes and other exception checking since it may allow for a faster cycle time of the processor than if this logic were implemented in the I-unit.
摘要翻译：在其执行单元（E单元）中具有检测要被执行的操作码和计算机制造商编程的操作码之间的匹配的计算机处理器提供了一种减轻处理器中的设计缺陷的方法。 E单元还包含用于将操作码和期望动作发送回指令单元（I单元）的机制，在该单元中可以将其与下一个被解码的指令进行比较。此外，E单元操作码比较逻辑包含用于打破可能导致的无限循环的机制。该E单元操作码比较机制也可用于其他目的，例如检测无效操作码和其他异常检查，因为与I单元中实现的逻辑相比，它可能允许处理器的周期更快。

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