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1. 发明申请

US20070196748A1 Process of making a semiconductor device using multiple antireflective materials 失效
标题翻译：制造使用多种抗反射材料的半导体器件的工艺
公开(公告)号：US20070196748A1
公开(公告)日：2007-08-23
申请号：US11356027
申请日：2006-02-17
申请人： Marie Angelopoulos , Katherina Babich , Sean Burns , Richard Conti , Allen Gabor , Scott Halle , Arpan Mahorowala , Dirk Pfeiffer
发明人： Marie Angelopoulos , Katherina Babich , Sean Burns , Richard Conti , Allen Gabor , Scott Halle , Arpan Mahorowala , Dirk Pfeiffer
IPC分类号： G03G13/00
CPC分类号： G03F7/091 , Y10S438/952
摘要： A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.
摘要翻译：一种光刻结构，主要由以下部分组成：设置在基板上的有机抗反射材料; 气相沉积的RCHX材料，其中R是选自Si，Ge，B，Sn，Fe和Ti中的一种或多种元素，并且其中X不存在或者是选自以下的一种或多种元素： O，N，S和F; 以及设置在RCHX材料上的光致抗蚀剂材料。本发明还涉及制造光刻结构的方法，并且使用该结构来图案化衬底。

2. 发明授权

US06247356B1 Hardness tester 有权
标题翻译：硬度计
公开(公告)号：US06247356B1
公开(公告)日：2001-06-19
申请号：US09281449
申请日：1999-03-30
申请人： John J. Merck, Jr. , Richard Conti , Joerg Meissner , Patrick Micozzi
发明人： John J. Merck, Jr. , Richard Conti , Joerg Meissner , Patrick Micozzi
IPC分类号： G01N342
CPC分类号： G01N3/42 , G01N2203/0082 , G01N2203/0482
摘要： A hardness tester having a frame and a rotatable turret movably supported on the frame is provided. A plurality of load cells are fixedly mountable on the turret, and a plurality of indenters are fixedly attachable to the load cells, respectively. A user interface selectively provides signals to a motor to move the turret into contact with a test specimen via one of the indenters to thereby apply a load on the test specimen. The indenters are fixed with respect to the turret and do not move in relation to the turret when the turret is brought down to bear on the test specimen. The load cells measure the load applied to the test specimen. A closed loop control system receives load measurement signals from the load cells and controls movement of the turret, preventing the motor from applying load in excess of a predetermined selectable load amount input by a user via the user interface. The invention preferably includes a plurality of indenter adapters, each attached to respective undersides of the load cells. Each indenter adapter includes a slot into which the indenter is fittable, and least one set screw for adjusting a horizontal location of the indenter.
摘要翻译：提供一种具有可移动地支撑在框架上的框架和可旋转转台的硬度计。多个测力传感器固定地安装在转台上，并且多个压头分别可固定地附接到测力传感器。用户界面选择性地向马达提供信号，以通过其中一个压头将转台移动到与试样接触，从而在测试样本上施加负载。压头相对于转台是固定的，并且当转盘被放在试样上时，它们不会相对于转台移动。称重传感器测量施加到试样上的载荷。闭环控制系统从负载传感器接收负载测量信号并控制转台的运动，从而防止电动机通过用户界面超过用户输入的预定可选负载量的负载。本发明优选地包括多个压头适配器，每个连接器连接到称重传感器的相应下侧。每个压头适配器包括可压入压头的槽，以及用于调节压头水平位置的至少一个固定螺钉。

3. 发明授权

US6142010A Penetration hardness tester 失效
标题翻译：渗透硬度计
公开(公告)号：US6142010A
公开(公告)日：2000-11-07
申请号：US821461
申请日：1997-03-21
申请人： John J. Merck, Jr. , Jon Wyman , Richard Conti
发明人： John J. Merck, Jr. , Jon Wyman , Richard Conti
IPC分类号： G01N3/00 , G01N3/42
CPC分类号： G01N3/42 , G01N2203/0082
摘要： A hardness tester is disclosed which conducts its hardness test through a penetrator impinging upon the surface of a test specimen. Enhanced accuracy and repeatability is achieved through the use of a closed loop system and directly mounting a load cell to the indentor, connecting a linear displacement transducer directly to the load cell and eliminating an elevating screw in initially positioning and applying load to the specimen to be tested.
摘要翻译：公开了一种通过撞击在试样表面上的穿透器来进行其硬度试验的硬度计。通过使用闭环系统并将称重传感器直接安装在压头上，可以实现提高的精度和重复性，将直线位移传感器直接连接到称重传感器，并消除升降螺钉初始定位并向样品施加载荷测试。

4. 发明授权

US4842418A Two temperature measuring probe 失效
标题翻译：两个温度测量探头
公开(公告)号：US4842418A
公开(公告)日：1989-06-27
申请号：US273614
申请日：1988-11-17
申请人： Richard Conti
发明人： Richard Conti
IPC分类号： G01K13/12 , G01N1/12 , G01N25/04 , G01N33/20
CPC分类号： G01N33/203 , G01K13/125 , G01N25/04 , G01N1/125 , Y10S73/09
摘要： A device for measuring both the phase change temperature of a sample of a molten metal bath and the actual bath temperature by means of a single thermocouple. The device having a chamber defined by a housing such that the housing will be consumed by the molten metal bath after determination of the phase change temperature of the sample within the chamber. After consumption of the housing, the sample remelts into the bath and the thermocouple determines the bath temperature.
摘要翻译：一种用于通过单个热电偶测量熔融金属浴样品和实际浴温度的相变温度的装置。该装置具有由壳体限定的室，使得在确定室内的样品的相变温度之后壳体将被熔融金属浴消耗。在外壳消耗后，样品再次熔化到浴中，热电偶决定浴温。

5. 发明申请

US20070048981A1 METHOD FOR PROTECTING A SEMICONDUCTOR DEVICE FROM CARBON DEPLETION BASED DAMAGE 审中-公开
标题翻译：用于保护基于碳沉积的损伤的半导体器件的方法
公开(公告)号：US20070048981A1
公开(公告)日：2007-03-01
申请号：US11162219
申请日：2005-09-01
申请人： Griselda Bonilla , Richard Conti , Timothy Dalton , Nicholas Fuller , Kelly Malone , Satyanarayana Nitta , Shom Ponoth
发明人： Griselda Bonilla , Richard Conti , Timothy Dalton , Nicholas Fuller , Kelly Malone , Satyanarayana Nitta , Shom Ponoth
IPC分类号： H01L21/04
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02304 , H01L21/02337 , H01L21/0234 , H01L21/76826
摘要： A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of carbon depletion as a result of the plasma based operation.
摘要翻译：用于保护半导体器件免受碳耗竭型损伤的方法包括用碳基材料富集多孔层间电介质材料（ILD）的暴露表面，以及对多孔ILD材料实施基于等离子体的操作。作为基于等离子体的操作的结果，多孔ILD材料的富集减少了碳耗竭的影响。

6. 发明授权

US5603988A Method for depositing a titanium or tantalum nitride or nitride silicide 失效
标题翻译：沉积钛或氮化钽或氮化硅硅化物的方法
公开(公告)号：US5603988A
公开(公告)日：1997-02-18
申请号：US459500
申请日：1995-06-02
申请人： Michael Shapiro , Ravi Kanjolia , Ben C. Hui , Paul F. Seidler , Karen Holloway , Richard Conti , Jonathan Chapple-Sokol
发明人： Michael Shapiro , Ravi Kanjolia , Ben C. Hui , Paul F. Seidler , Karen Holloway , Richard Conti , Jonathan Chapple-Sokol
IPC分类号： C23C16/18 , C23C16/34 , C23C16/42
CPC分类号： C23C16/18 , C23C16/34
摘要： Titanium and/or tantalum nitrides or nitride silicides are deposited onto a substrate by chemical vapor deposition of a titanium and/or tantalum silylamido complex.
摘要翻译：钛和/或钽氮化物或氮化硅硅化物通过化学气相沉积钛和/或钽硅烷酰氨基复合物沉积到基底上。

7. 发明申请

US20080045039A1 METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE 失效
公开(公告)号：US20080045039A1
公开(公告)日：2008-02-21
申请号：US11873721
申请日：2007-10-17
申请人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
发明人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

8. 发明申请

US20070004206A1 IMPROVED HDP-BASED ILD CAPPING LAYER 有权
标题翻译：改进的基于HDP的ILD捕获层
公开(公告)号：US20070004206A1
公开(公告)日：2007-01-04
申请号：US11467593
申请日：2006-08-28
申请人： Yun-Yu Wang , Richard Conti , Chung-Ping Eng , Matthew Nicholls
发明人： Yun-Yu Wang , Richard Conti , Chung-Ping Eng , Matthew Nicholls
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.
摘要翻译：一种覆盖氮化物叠层，可以防止蚀刻渗透到HDP氮化物，同时保持在Cu顶部的HDP氮化物的电迁移效果。在一个实施例中，堆叠包括第一层HDP氮化物和设置在第一层上的Si-C-H化合物的第二层。 Si-C-H化合物例如是BLoK或N-BLoK（Si-C-H-N），并且选自在通孔RIE期间具有高选择性的一组材料，使得来自下一个布线层的RIE化学不会穿透。碳氮是关键要素。在另一个实施例中，堆叠包括第一层HDP氮化物，随后是第二层UVN（等离子体氮化物），以及包含设置在第二层上的HDP氮化物的第三层。

9. 发明申请

US20050200056A1 Apparatus and method for determining fluid depth 审中-公开
标题翻译：用于确定流体深度的装置和方法
公开(公告)号：US20050200056A1
公开(公告)日：2005-09-15
申请号：US11078497
申请日：2005-03-11
申请人： Richard Conti
发明人： Richard Conti
IPC分类号： C21D11/00
CPC分类号： C21C5/4673 , C21C2005/5288 , F27D21/0028 , Y02P10/216
摘要： A fluid depth determination system is provided for a vessel that contains first and second immiscible fluids, where the second fluid floats on top of the first fluid forming an interface therebetween. The system includes a first pressure probe which is located in the floor of the vessel, a second pressure probe being at least vertically moveable in the first and second fluids in a region of the interface, means for collecting pressure readings from the first and second pressure probes and means for calculating the depth of the first fluid based on a difference in the pressure readings. The present invention is also directed to a method of determining a depth of a first fluid having an immiscible second fluid floating on top of the first fluid and forming an interface therebetween.
摘要翻译：为包含第一和第二不混溶流体的容器提供流体深度确定系统，其中第二流体浮在第一流体的顶部上，形成其间的界面。该系统包括位于容器底部的第一压力探针，在界面的区域中至少可在第一和第二流体中垂直移动的第二压力探针，用于从第一和第二压力收集压力读数的装置探针和用于基于压力读数的差计算第一流体的深度的装置。本发明还涉及一种确定第一流体的深度的方法，该第一流体具有漂浮在第一流体的顶部上并且在其间形成界面的不混溶的第二流体。

10. 发明申请

US20050079701A1 METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH COMPRESSIVE DIFFUSION BARRIER MATERIAL 有权
标题翻译：利用压缩扩散阻挡材料形成平面材料的平均结构形成方法
公开(公告)号：US20050079701A1
公开(公告)日：2005-04-14
申请号：US10905068
申请日：2004-12-14
申请人： Heidi Baks , Richard Bruff , Richard Conti , Allan Upham
发明人： Heidi Baks , Richard Bruff , Richard Conti , Allan Upham
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76804
摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.
摘要翻译：本发明涉及集成电路器件中的双镶嵌互连结构的制造。具体地，公开了一种利用平面化材料和压缩扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。阻挡材料优选具有大于300MPa的压缩应力。在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。然后可以将所得的双镶嵌结构金属化。通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

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