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1. 发明申请

US20120139764A1 Continuous Time Sigma-Delta ADC with Embedded Low-Pass Filter 有权
标题翻译：具有嵌入式低通滤波器的连续时间Sigma-Delta ADC
公开(公告)号：US20120139764A1
公开(公告)日：2012-06-07
申请号：US13310587
申请日：2011-12-02
申请人： Marco Sosio , Antonio Liscidini , Rinaldo Castello , Gabriele Gandolfi , Vittorio Colonna
发明人： Marco Sosio , Antonio Liscidini , Rinaldo Castello , Gabriele Gandolfi , Vittorio Colonna
IPC分类号： H03M3/02 , H03M1/36 , H03M1/12
CPC分类号： H03M1/06 , H03M3/344 , H03M3/368 , H03M3/424 , H03M3/454 , H03M3/456
摘要： A filtering analog to digital converter (ADC) includes an integrator receiving at its input an analog input signal. A filtering capacitor at the input of the integrator filters out a large portion of out-of-band interferers in the analog input signal. The integrator produces an output that is quantized to produce a digital output. A feedback path between the quantizer output and the integrator input includes a digital to analog converter (DAC).
摘要翻译：滤波模数转换器（ADC）包括积分器，在其输入端接收模拟输入信号。积分器输入端的滤波电容滤除模拟输入信号中的大部分带外干扰源。积分器产生一个被量化以产生数字输出的输出。量化器输出和积分器输入之间的反馈路径包括数模转换器（DAC）。

2. 发明授权

US08581762B2 Continuous time sigma-delta ADC with embedded low-pass filter 有权
标题翻译：具有嵌入式低通滤波器的连续时间Σ-ΔADC
公开(公告)号：US08581762B2
公开(公告)日：2013-11-12
申请号：US13310587
申请日：2011-12-02
申请人： Marco Sosio , Antonio Liscidini , Rinaldo Castello , Gabriele Gandolfi , Vittorio Colonna
发明人： Marco Sosio , Antonio Liscidini , Rinaldo Castello , Gabriele Gandolfi , Vittorio Colonna
IPC分类号： H03M3/00
CPC分类号： H03M1/06 , H03M3/344 , H03M3/368 , H03M3/424 , H03M3/454 , H03M3/456
摘要： A filtering analog to digital converter (ADC) includes an integrator receiving at its input an analog input signal. A filtering capacitor at the input of the integrator filters out a large portion of out-of-band interferers in the analog input signal. The integrator produces an output that is quantized to produce a digital output. A feedback path between the quantizer output and the integrator input includes a digital to analog converter (DAC).
摘要翻译：滤波模数转换器（ADC）包括积分器，在其输入端接收模拟输入信号。积分器输入端的滤波电容滤除模拟输入信号中的大部分带外干扰源。积分器产生一个被量化以产生数字输出的输出。量化器输出和积分器输入之间的反馈路径包括数模转换器（DAC）。

3. 发明授权

US08165555B1 Method and apparatus for filtering 有权
标题翻译：过滤方法和装置
公开(公告)号：US08165555B1
公开(公告)日：2012-04-24
申请号：US12372215
申请日：2009-02-17
申请人： Fernando De Bernardinis , Rinaldo Castello
发明人： Fernando De Bernardinis , Rinaldo Castello
IPC分类号： H04B1/10
CPC分类号： H04B1/18 , H03F2200/91 , H03F2203/45026 , H03H11/1213 , H03H11/1291
摘要： Aspects of the disclosure can provide a second order low pass filter. The second order low pass filter can work in current domain, and have high linearity for in-band signals and out-of-band signals. The second order low pass filter can include a MOS transistor having a gate terminal, a current input terminal and a current output terminal, a first capacitor coupled between the current input terminal and a ground connection and a second capacitor coupled between the gate terminal and the current input terminal.
摘要翻译：本公开的方面可以提供二阶低通滤波器。二阶低通滤波器可以在当前领域工作，并且对于带内信号和带外信号具有高线性度。二阶低通滤波器可以包括具有栅极端子，电流输入端子和电流输出端子的MOS晶体管，耦合在电流输入端子和接地连接器之间的第一电容器和耦合在栅极端子和电流输出端子之间的第二电容器电流输入端子。

4. 发明授权

US06424172B1 Circuit structure for synthesizing time-continual filters 有权
标题翻译：用于合成时间连续滤波器的电路结构
公开(公告)号：US06424172B1
公开(公告)日：2002-07-23
申请号：US09796996
申请日：2001-02-28
申请人： Valerio Pisati , Salvatore Portaluri , Marco Cazzaniga , Rinaldo Castello
发明人： Valerio Pisati , Salvatore Portaluri , Marco Cazzaniga , Rinaldo Castello
IPC分类号： H03K19082
CPC分类号： H03H11/0422
摘要： This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor. Thus, a released “zero” can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
摘要翻译：本发明涉及具有可编程零点的前馈类型的电路结构，特别是用于合成时间连续滤波器。该结构包括互连至少一个互连节点并连接在第一单元的第一信号输入和第二单元的输出端之间的一对放大单元，每个单元包括一对具有共同的导通端子并具有其它导电端子通过相应的偏置构件分别耦合到第一电压基准。所述结构还包括将所述第一单元的节点连接到所述输出端子并且包括具有连接到所述第一单元的节点的控制端子的晶体管，连接到所述输出端子的第一导通端子和第二导通端子通过电容器耦合到第二参考电压。因此，可以在极零复平面的右半平面中引入释放的“零”，以改善组增益的平坦化。

5. 发明授权

US5994960A High speed switched op-amp for low supply voltage applications 失效
标题翻译：用于低电源电压应用的高速开关运算放大器
公开(公告)号：US5994960A
公开(公告)日：1999-11-30
申请号：US948562
申请日：1997-10-10
申请人： Andrea Baschirotto , Angelo Nagari , Rinaldo Castello
发明人： Andrea Baschirotto , Angelo Nagari , Rinaldo Castello
IPC分类号： H03F1/08 , H03F3/72 , H03F3/45 , H03F1/14
CPC分类号： H03F3/72 , H03F1/086 , H03F2200/513
摘要： In a switched operational amplifier including a differential input stage and at least a second output stage, the compensation capacitor commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with a switching circuit. The switching circuit is controlled by the same control phase that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.
摘要翻译：在包括差分输入级和至少第二输出级的开关运算放大器中，将第二级的输出节点与放大器的输入差分级的相应输出节点耦合起来的补偿电容器与切换电路。开关电路由相同的控制相位控制，使得放大器能够在禁止放大器以减少开关电流的相位期间中断补偿电容器（CC）和差分输入级的输出节点之间的连接，准时。值得注意的是，运算放大器的差分输入级保持始终有效，只有第二个输出级接通和关断。

6. 发明授权

US5834976A Frequency self-compensated operational amplifier 失效
标题翻译：频率自补偿运算放大器
公开(公告)号：US5834976A
公开(公告)日：1998-11-10
申请号：US756024
申请日：1996-11-26
申请人： Luciano Tomasini , Rinaldo Castello , Giancarlo Clerici , Ivan Bietti
发明人： Luciano Tomasini , Rinaldo Castello , Giancarlo Clerici , Ivan Bietti
IPC分类号： H03F1/08 , H03F1/14 , H03F1/34
CPC分类号： H03F1/086
摘要： An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage and an amplifier output stage connected serially together to receive an input signal on at least one input terminal of the amplifier and generate an amplified signal on an output terminal of the amplifier. Provided between the input and output stages is an intermediate node which is connected to a compensation block to receive a frequency-variable compensation signal therefrom. The compensation block is coupled with its input to the input terminal of the amplifier The compensation block is connected to receive at least the feedback signal. Preferably, the compensation signal is variable as a function of a gain value which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value.
摘要翻译：相对于闭环增益自补偿的运算放大器频率包括跨导输入级和串联连接的放大器输出级，以在放大器的至少一个输入端上接收输入信号，并在输出端产生放大信号的放大器。在输入级和输出级之间设置有中间节点，其连接到补偿块以从其接收频率可变的补偿信号。补偿块与其输入耦合到放大器的输入端子。补偿块被连接以至少接收反馈信号。优选地，补偿信号作为由反馈电路确定的增益值的函数而变化，并且补偿信号的所述变化以与增益值成反比关系的关系发生。

7. 发明授权

US5528683A Method and circuit for implementing an impedance, in particular for DC telephonic applications 失效
标题翻译：用于实现阻抗的方法和电路，特别是用于DC电话应用
公开(公告)号：US5528683A
公开(公告)日：1996-06-18
申请号：US425228
申请日：1995-04-17
申请人： Luciano Tomasini , Rinaldo Castello
发明人： Luciano Tomasini , Rinaldo Castello
IPC分类号： H03F3/343 , H03F3/347 , H03H11/48 , H04B1/58 , H04M1/58 , H04M1/76 , H04M1/00
CPC分类号： H04M1/76 , H04B1/586 , H04M1/585
摘要： The invention relates to a method and circuit for implementing an impedance associated with a monolithically integrated telephone subscriber circuit connected to a telephone line having a pair of terminals. The circuit consists of a resistor connected serially to one terminal of the telephone line, and a series of current mirror circuits. The current mirror circuits are connected in a closed loop configuration to the one terminal of the telephone line. The current mirror circuits divide, by a predetermined factor, the value of the resistor when a DC or very low frequency signal is input to the telephone circuit.
摘要翻译：本发明涉及一种用于实现与连接到具有一对终端的电话线的单片电话用户电路相关联的阻抗的方法和电路。该电路包括串联连接到电话线的一个端子的电阻器和一系列电流镜电路。电流镜电路以闭环配置连接到电话线的一个终端。电流镜电路将DC或极低频信号输入到电话电路时以预定的因数除以电阻的值。

8. 发明授权

US5136258A Circuit arrangement for enhancing the transconductance of a differential amplifier stage comprising MOS transistors 失效
标题翻译：用于增强包括MOS晶体管的差分放大器级的跨导的电路装置
公开(公告)号：US5136258A
公开(公告)日：1992-08-04
申请号：US768457
申请日：1991-09-30
申请人： Germano Nicollini , Rinaldo Castello
发明人： Germano Nicollini , Rinaldo Castello
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F3/45076 , H03F3/45183 , H03F2203/45026 , H03F2203/45036 , H03F2203/45192 , H03F2203/45251 , H03F2203/45288 , H03F2203/45318 , H03F2203/45658
摘要： A circuit arrangement for enhancing the transconductance of a differential amplifier stage comprising a pair of MOS transistors, having respective source electrodes connected together through a circuit node, comprises a pair of active components respectively connected in each of the connections between the aforesaid electrodes and the aforesaid node and serving a characteristic function corresponding to that of a negative value resistor. This arrangement enables the transconductance of the differential stage to be increased while keeping the dissipated electric power low and the area occupied in an integrated circuit small.
摘要翻译：一种用于增强包括一对MOS晶体管的差分放大器级的跨导的电路装置，其具有通过电路节点连接在一起的各个源极，包括分别连接在上述电极和上述电极之间的每个连接中的一对有源元件并提供与负值电阻器相对应的特征函数。这种布置使得能够增加差分级的跨导，同时保持耗散的功率低并且集成电路中占据的面积小。

9. 发明授权

US08868015B2 Transmit architecture for wireless multi-mode applications 有权
标题翻译：无线多模应用的传输体系结构
公开(公告)号：US08868015B2
公开(公告)日：2014-10-21
申请号：US12782848
申请日：2010-05-19
申请人： Gregory Uehara , Chao Yang , Ruoxin Jiang , Fernando De Bernardinis , Alessandro Venca , Rinaldo Castello , Marc Leroux , Brian Brunn
发明人： Gregory Uehara , Chao Yang , Ruoxin Jiang , Fernando De Bernardinis , Alessandro Venca , Rinaldo Castello , Marc Leroux , Brian Brunn
IPC分类号： H04B1/04 , H04B1/00
CPC分类号： H04B1/0071
摘要： In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.
摘要翻译：在一个实施例中，一种装置包括上变频单元，其被配置为将基带信号上变频到射频（RF）信号。提供了多个用于多个无线频段的不平衡变压器。多路复用电路耦合到多个不平衡转换器，其中上转换单元通过复用电路耦合到每个平衡 - 不平衡变换器。复用电路被配置为基于所使用的无线频带将来自上变频单元的射频信号复用到多个巴伦中的一个。

10. 发明授权

US6031416A First and second order CMOS elementary cells for time-continuous analog filters 失效
标题翻译：用于时间连续模拟滤波器的一阶和二阶CMOS单元
公开(公告)号：US6031416A
公开(公告)日：2000-02-29
申请号：US67127
申请日：1998-04-27
申请人： Andrea Baschirotto , Ugo Baschirotto , Guido Brasca , Rinaldo Castello
发明人： Andrea Baschirotto , Ugo Baschirotto , Guido Brasca , Rinaldo Castello
IPC分类号： H03H11/04 , H03K5/00
CPC分类号： H03H11/04
摘要： A CMOS elementary cell of the first order for time-continuous analog filters with non-linearity compensation, is connected between a first supply voltage reference and a second voltage reference. The cell is of a type which comprises at least a first MOS transistor having its conduction terminals connected to the first supply voltage reference and to an output terminal, and having a control terminal connected to an input terminal of the first order CMOS elementary cell. The cell further comprises a second MOS transistor in diode configuration, and an equivalent capacitor, both connected to the output terminal of the first order CMOS elementary cell. The second, diode-connected MOS transistor and the equivalent capacitor act as a load for the first MOS transistor. The first MOS transistor operates as a drive transistor operatively tied to an input voltage signal being supplied to the input terminal of the first order CMOS elementary cell. A second order filter CMOS elementary cell is similarly connected.
摘要翻译：具有非线性补偿的时间连续模拟滤波器的第一阶CMOS元件连接在第一电源电压基准和第二参考电压之间。电池是至少包括其导通端子连接到第一电源电压基准的第一MOS晶体管和输出端子，并且具有连接到第一级CMOS基本单元的输入端子的控制端子的类型。电池还包括二极管配置的第二MOS晶体管和等效电容器，两者均连接到一阶CMOS元件单元的输出端子。第二个二极管连接的MOS晶体管和等效电容器用作第一MOS晶体管的负载。第一MOS晶体管作为驱动晶体管工作，该驱动晶体管可操作地连接到被提供给第一阶CMOS元件单元的输入端的输入电压信号。类似地连接二阶滤波器CMOS单元。

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