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1. 发明授权

US09041153B2 MIM capacitor having a local interconnect metal electrode and related structure 有权
标题翻译：具有局部互连金属电极和相关结构的MIM电容器
公开(公告)号：US09041153B2
公开(公告)日：2015-05-26
申请号：US13248823
申请日：2011-09-29
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
IPC分类号： H01L29/92 , H01L23/522 , H01L49/02
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
摘要翻译：根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器形成在底部电容器电极上的层间势垒电介质上的电极。顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。在一个实施例中，底部电容器电极由栅极金属形成。该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

2. 发明授权

US08048765B2 Method for fabricating a MOS transistor with source/well heterojunction and related structure 有权
公开(公告)号：US08048765B2
公开(公告)日：2011-11-01
申请号：US12583977
申请日：2009-08-28
申请人： Xiangdong Chen , Bruce Chih-Chieh Shen , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Bruce Chih-Chieh Shen , Henry Kuo-Shun Chen
IPC分类号： H01L21/76
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0856 , H01L29/086 , H01L29/165 , H01L29/267 , H01L29/6656 , H01L29/66689 , H01L29/7848
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.

3. 发明申请

US20130082351A1 Method for Fabricating a MIM Capacitor Having a Local Interconnect Metal Electrode and Related Structure 有权
标题翻译：具有局部互连金属电极和相关结构的MIM电容器的制造方法
公开(公告)号：US20130082351A1
公开(公告)日：2013-04-04
申请号：US13248823
申请日：2011-09-29
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
摘要翻译：根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器形成在底部电容器电极上的层间势垒电介质上的电极。顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。在一个实施例中，底部电容器电极由栅极金属形成。该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

4. 发明申请

US20110169079A1 Semiconductor device having an overlapping multi-well implant and method for fabricating same 审中-公开
标题翻译：具有重叠多孔注入的半导体器件及其制造方法
公开(公告)号：US20110169079A1
公开(公告)日：2011-07-14
申请号：US12657162
申请日：2010-01-14
申请人： Akira Ito , Henry Kuo-Shun Chen , Bruce Chih-Chieh Shen
发明人： Akira Ito , Henry Kuo-Shun Chen , Bruce Chih-Chieh Shen
IPC分类号： H01L29/78 , H01L21/30
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device having an overlapping multi-well implant comprises an isolation structure formed in a semiconductor body, a first well implant formed in the semiconductor body surrounding the isolation structure, and a second well implant overlapping at least a portion of the first well implant. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise a gate formed over the semiconductor body adjacent to the isolation structure, wherein the first well implant extends a first lateral distance under the gate and the second well implant extends a second lateral distance under the gate, and wherein the first and second lateral distances may be different. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including a power management circuit or a power amplifier.
摘要翻译：根据一个实施例，具有重叠多阱注入的半导体器件包括形成在半导体本体中的隔离结构，形成在半导体主体中的围绕隔离结构的第一阱注入，以及重叠至少部分第一口植入物。所公开的可以是NMOS或PMOS器件的半导体器件还可以包括形成在半导体主体上方的与隔离结构相邻的栅极，其中第一阱注入在栅极下延伸第一横向距离，第二阱注入延伸一个栅极下方的第二横向距离，并且其中第一和第二横向距离可以不同。在一个实施例中，所公开的半导体器件被制造为包括功率管理电路或功率放大器的集成电路的一部分。

5. 发明申请

US20110049620A1 Method for fabricating a MOS transistor with source/well heterojunction and related structure 有权
标题翻译：用于制造具有源/阱异质结及相关结构的MOS晶体管的方法
公开(公告)号：US20110049620A1
公开(公告)日：2011-03-03
申请号：US12583977
申请日：2009-08-28
申请人： Xiangdong Chen , Bruce Chih-Chieh Shen , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Bruce Chih-Chieh Shen , Henry Kuo-Shun Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0856 , H01L29/086 , H01L29/165 , H01L29/267 , H01L29/6656 , H01L29/66689 , H01L29/7848
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在阱上形成栅极堆叠。所述方法还包括在所述阱中形成与所述栅极堆叠的第一侧壁相邻的凹部。该方法还包括在凹部中形成源极区域，使得在源区域和阱之间形成异质结。该方法还包括形成与栅极堆叠的第二侧壁间隔开的漏极区域。在一个实施例中，源极区域可以包括硅锗，并且阱可以包括硅。在另一个实施例中，源极区域可以包括碳化硅，阱可以包括硅。

6. 发明授权

US07078786B1 Composite series resistor having reduced temperature sensitivity in an IC chip 有权
标题翻译：复合串联电阻在IC芯片中具有降低的温度灵敏度
公开(公告)号：US07078786B1
公开(公告)日：2006-07-18
申请号：US10843190
申请日：2004-05-10
申请人： Marco Racanelli , Chun Hu , Chih-Chieh Shen
发明人： Marco Racanelli , Chun Hu , Chih-Chieh Shen
IPC分类号： H01L29/00
CPC分类号： H01L28/24 , H01L27/0802 , H01L28/20
摘要： According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. According to this exemplary embodiment, the integrated circuit chip further comprises a metal resistor having a first terminal and a second terminal, where the metal resistor is situated over the poly resistor, and where the first terminal of the metal resistor is connected to the first terminal of the poly resistor. According to this exemplary embodiment, the integrated circuit chip may further comprise a first metal segment connected to the second terminal of the metal resistor and a second metal segment connected to the second terminal of the poly resistor. The integrated circuit chip may further comprise an inter-layer dielectric situated between the poly resistor and the metal resistor.
摘要翻译：根据一个示例性实施例，集成电路芯片包括氧化物区域。集成电路芯片还包括具有第一端子和第二端子的聚电阻器，其中多晶硅电阻器位于氧化物区域上方。根据该示例性实施例，集成电路芯片还包括具有第一端子和第二端子的金属电阻器，其中金属电阻器位于多晶硅电阻器上方，并且金属电阻器的第一端子连接到第一端子的聚电阻。根据该示例性实施例，集成电路芯片还可以包括连接到金属电阻器的第二端子的第一金属段和连接到多晶硅电阻器的第二端子的第二金属段。集成电路芯片还可以包括位于多个电阻器和金属电阻器之间的层间电介质。

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