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1. 发明授权

US06769033B1 Network processor processing complex and methods 失效
标题翻译：网络处理器处理复杂和方法
公开(公告)号：US06769033B1
公开(公告)日：2004-07-27
申请号：US09384691
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F900
CPC分类号： H04L49/602 , G06F15/80 , H04L49/351
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过嵌入式处理器复合体与一组外围设备的协作来增强数据流处理和灵活性，这些外围设备都形成在公共半导体衬底上。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成于半导体衬底上的指令存储器中的指令的控制下操作，同时由存储器外围设备和与外部存储器元件的接口提供过渡数据流部分的存储。

2. 发明授权

US06588008B1 Assembler tool for processor-coprocessor computer systems 失效
标题翻译：处理器 - 协处理器计算机系统的汇编工具
公开(公告)号：US06588008B1
公开(公告)日：2003-07-01
申请号：US09546755
申请日：2000-04-11
申请人： Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F945
CPC分类号： G06F9/30043 , G06F8/47 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/3885
摘要： A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.
摘要翻译：一种中央处理器 - 协处理器组件，其包括用于将基本中央处理器任务扩展到至少一个协处理器的汇编器软件工具。重要的是，当对协处理器元素进行更改时，汇编程序软件工具不需要重新构建。本发明允许基本核心语言处理（CLP）编程模型的组装时间扩展，而不需要重建汇编器工具本身。汇编器工具包括使得中央处理器能够操纵协处理器寄存器的一组命令，以及协处理器执行指令，其在协处理器上启动命令处理。本发明通过使得硬件设计者能够更新其协处理器定义文件以反映新的或修改的协处理器，通过多个硬件修订来简化了汇编工具的维护。

3. 发明授权

US06829697B1 Multiple logical interfaces to a shared coprocessor resource 失效
标题翻译：到共享协处理器资源的多个逻辑接口
公开(公告)号：US06829697B1
公开(公告)日：2004-12-07
申请号：US09656582
申请日：2000-09-06
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F1500
CPC分类号： G06F15/7864
摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.
摘要翻译：嵌入式处理器复合体包含多个协议处理器单元（PPU）。每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。

4. 发明授权

US06760743B1 Instruction memory system for multi-processor environment and disjoint tasks 有权
标题翻译：指令存储系统，用于多处理器环境和不相交任务
公开(公告)号：US06760743B1
公开(公告)日：2004-07-06
申请号：US09477757
申请日：2000-01-04
申请人： Marco C. Heddes , Mark Anthony Rinaldi , Brian Alan Youngman
发明人： Marco C. Heddes , Mark Anthony Rinaldi , Brian Alan Youngman
IPC分类号： G06F900
CPC分类号： G06F9/3802 , G06F9/3851
摘要： An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space is divided into code segments according to the disjoint tasks to be performed. The instruction codes of each processor are consolidated into one copy for control instructions and duplicate copies for other disjoint tasks such as inbound requests and outbound requests that have greater processor contention. Interleaving of the memory arrays for certain disjoint tasks serves to provide a larger number of instructions for these tasks. The system utilizes arbiters to receive all disjoint tasks and to control multiplexors that send addresses to memory arrays.
摘要翻译：指令存储器系统由多个处理器共享，并且系统利用增加的带宽来支持组合的处理器数量。总指令地址空间根据要执行的不相交任务分为代码段。每个处理器的指令代码被合并到一个副本中，用于控制指令和其他不相交任务的重复副本，例如具有更大处理器争用的入站请求和出站请求。用于某些不相交任务的存储器阵列的交织用于为这些任务提供更多数量的指令。该系统利用仲裁器接收所有不相交的任务，并控制向存储器阵列发送地址的多路复用器。

5. 发明授权

US07107265B1 Software management tree implementation for a network processor 失效
标题翻译：网络处理器的软件管理树实现
公开(公告)号：US07107265B1
公开(公告)日：2006-09-12
申请号：US09545100
申请日：2000-04-06
申请人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi
发明人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi
IPC分类号： G06F17/30 , G06F15/00 , G06F9/44
CPC分类号： H04L45/742 , G06F17/30961 , G06F17/30985 , Y10S707/99933 , Y10S707/99936 , Y10S707/99937
摘要： Novel data structures, methods and apparatus for a Software Managed Tree (SMT) which provides a mechanism to create tree structures that follow a search mechanism defined by a control point processor. The search mechanism does not require storage on the previous pointer and uses only a forward pointer along with a next bit or group of bits to test thereby reducing storage space for nodes. The search mechanism processes multiple filter rules for an application without requiring multiple searches and also allows various filter rules to be chained. Two patterns of the same length are stored in each leaf to define a range compare. A compare at the end operation is either a compare under range or a compare under mask. In a compare under range, the input key is checked to determine if it is in the range defined by the two patterns. In a compare under mask, the bits in the input key are compared with the bits in a first leaf pattern under a mask specified in a second leaf pattern.
摘要翻译：用于软件管理树（SMT）的新型数据结构，方法和装置，其提供了一种机制，用于创建遵循由控制点处理器定义的搜索机制的树结构。搜索机制不需要在前一个指针上存储，并且仅使用前向指针以及下一个位或一组位来进行测试，从而减少节点的存储空间。搜索机制处理应用程序的多个过滤器规则，而不需要多次搜索，并且还允许链接各种过滤器规则。在每个叶中存储相同长度的两个图案以定义范围比较。在最终操作中的比较是在范围之下的比较或掩码下的比较。在范围比较范围内，检查输入键以确定是否在两种模式定义的范围内。在掩码下的比较中，将输入密钥中的比特与在第二叶图案中指定的掩码下的第一叶图案中的比特进行比较。

6. 发明授权

US06898179B1 Network processor/software control architecture 失效
标题翻译：网络处理器/软件控制架构
公开(公告)号：US06898179B1
公开(公告)日：2005-05-24
申请号：US09544896
申请日：2000-04-07
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Mark Anthony Rinaldi , Michael Steven Siegel , Colin Beaton Verrilli , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Mark Anthony Rinaldi , Michael Steven Siegel , Colin Beaton Verrilli , Fabrice Jean Verplanken
IPC分类号： G06F11/00 , H04B7/216 , H04L1/16 , H04L12/26
CPC分类号： G06F15/17
摘要： The transport protocol for communicating between general purpose processors acting as contact points and network processors in a packet processing environment such as Ethernet is provided. In such an environment, there is at least one single control point processor (CP) and a plurality of network processors (NP), sometimes referred to as blades. A typical system could contain two to sixteen network processors, and each network processor connects to a plurality of devices which communicate with each other over a network transport, such as Ethernet. The CP typically controls the functionality and the functioning of the network processors to function in a way that connects one end user with another, whether or not the end user is on the same network processor or a different network processor. There are three types of communication provided; first, there is communication generally referred to as control services and normally there will be only one pico processor which operates as a GCH (guided cell handler) and only one that operates as a guided tree handler (GTH). A path is provided for the controls to the GCH and the GTH commands, and a separate path is provided for the data frames between the GDH's (general data handler) and the CP.
摘要翻译：提供了用于在诸如以太网的分组处理环境中用作接触点的通用处理器和网络处理器之间进行通信的传输协议。在这样的环境中，存在至少一个单个控制点处理器（CP）和多个网络处理器（NP），有时称为刀片。典型的系统可以包含两到十六个网络处理器，并且每个网络处理器连接到通过诸如以太网的网络传输彼此通信的多个设备。 CP通常控制网络处理器的功能和功能，以使终端用户与另一终端用户相连的方式起作用，无论终端用户是否在同一个网络处理器或不同的网络处理器上。提供三种通讯方式; 首先，通常被称为控制服务的通信，并且通常将只有一个微微处理器作为GCH（引导的单元处理器）操作，并且只有一个作为引导树处理器（GTH）操作。为GCH和GTH命令的控制提供路径，并为GDH（通用数据处理程序）和CP之间的数据帧提供单独的路径。

7. 发明授权

US06498781B1 Self-tuning link aggregation system 失效
标题翻译：自调整链路聚合系统
公开(公告)号：US06498781B1
公开(公告)日：2002-12-24
申请号：US09374003
申请日：1999-08-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Loren Douglas Larsen , Jeffrey James Lynch , Mark Anthony Rinaldi , Michael Steven Siegel
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Loren Douglas Larsen , Jeffrey James Lynch , Mark Anthony Rinaldi , Michael Steven Siegel
IPC分类号： H04L1226
CPC分类号： H04L41/5025 , H04L43/0829 , H04L43/16
摘要： A data processing system and method in a computer network are disclosed for improving performance of a link aggregation system included in the network. Parameters are established which are utilized to determine performance criteria of the link aggregation system. A performance of the link aggregation system is determined by determining the performance criteria. The performance of the link aggregation system changes in response to a flow traffic burden on the link aggregation system changing. The link aggregation system dynamically modifies the parameters in response to the changing performance of the link aggregation system. The link aggregation system is self-tuning and capable of automatically adjusting to a changing flow traffic burden on the link aggregation system.
摘要翻译：公开了一种计算机网络中的数据处理系统和方法，用于改善网络中包括的链路聚合系统的性能。建立了用于确定链路聚合系统性能标准的参数。通过确定性能标准来确定链路聚合系统的性能。链路聚合系统的性能响应链路聚合系统的流量负担变化而变化。链路聚合系统根据链路聚合系统的性能变化动态修改参数。链路聚合系统是自调整的，能够自动调整链路聚合系统上流量流量负担的变化。

8. 发明授权

US06728253B1 Mixed queue scheduler 失效
标题翻译：混合队列调度程序
公开(公告)号：US06728253B1
公开(公告)日：2004-04-27
申请号：US09405691
申请日：1999-09-24
申请人： Clark Debs Jeffries , Marco C. Heddes , Mark Anthony Rinaldi , Michael Steven Siegel
发明人： Clark Debs Jeffries , Marco C. Heddes , Mark Anthony Rinaldi , Michael Steven Siegel
IPC分类号： H04L1256
CPC分类号： H04L47/50 , H04L2012/5682
摘要： A method and system are disclosed for allocating data input bandwidth from a source link to a plurality of N data queues each having a variable occupancy value, Qi(t), and a constant decrement rate, Di, where i designated the ith queue among the N queues. First, a threshold occupancy value, T, is designated for the N queues. During each time step of a repeating time interval, &Dgr;t, the occupancy value, Qi, is compared with T. In response to each and every of said N data queues having occupancy values exceeding T, pausing data transmission from the source link to the N data queues, such that overflow within the data queues is minimized. In response to at least one of the N data queues having an occupancy value less than or equal to T, selecting one among the N data queues to be incremented, and incrementing the selected data queue, such that underflow of the selected queue is minimized. In the context of scheduling one cell per time step, the value of T is one. Furthermore, the method of the present invention guarantees that output port occupancy shall never, in that context, exceed two cells.
摘要翻译：公开了一种用于将数据输入带宽从源链路分配给多个N个数据队列的方法和系统，每个N个数据队列具有可变占用值Qi（t）和常数递减率Di，其中i指定i < 排队N队列。首先，为N个队列指定阈值占有率T。在重复时间间隔的每个时间步长，Deltat，占用值Qi与T进行比较。响应于具有超过T的占用值的所述N个数据队列中的每一个，暂停从源链路到N的数据传输数据队列，使数据队列中的溢出最小化。响应于具有小于或等于T的占用值的N个数据队列中的至少一个，选择要增加的N个数据队列中的一个，并增加所选择的数据队列，使得所选队列的下溢最小化。在每个时间步长调度一个单元格的上下文中，T的值为1。此外，本发明的方法保证输出端口占用在这方面永远不超过两个小区。

9. 发明授权

US06298340B1 System and method and computer program for filtering using tree structure 失效
标题翻译：使用树结构进行过滤的系统和方法以及计算机程序
公开(公告)号：US06298340B1
公开(公告)日：2001-10-02
申请号：US09312148
申请日：1999-05-14
申请人： Jean Louis Calvignac , Everett Arthur Corl, Jr. , Anthony Matteo Gallo , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi , Colin Beaton Verrilli
发明人： Jean Louis Calvignac , Everett Arthur Corl, Jr. , Anthony Matteo Gallo , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi , Colin Beaton Verrilli
IPC分类号： G06F1730
CPC分类号： G06F17/30961 , Y10S707/99931 , Y10S707/99933 , Y10S707/99943 , Y10S707/99944
摘要： A classification system includes a software managed tree testing bits from a key which labels an item. The bits are chosen by application of the Choice Bit Algorithm to the Rules in a Database of Rules. A controller including logic parses an unknown Key for bits to be tested in the decision nodes of a binary tree. Tests dictated by the tree are conducted in a predetermined way until all but one Rule from the database or all but a few Rules from the database are eliminated from consideration, whereupon the Key is fully tested by the one remaining Rule or in a lattice constructed of the remaining plurality of Rules, to determine an action to enforce on the item. Certain compare tests are used in the binary tree for the case that otherwise identical or similar rules are applied to integer ranges of key values which do not fall upon power of 2 boundaries. Furthermore, some very frequently occurring rules in such final tests might be designated as secondary rules, the remaining rules designated as primary rules, the entire decision tree recalculated using only primary rules, and the primary rules then connected to secondary rules only when logically necessary by means of a system of pointers making use of relative priorities of rules.
摘要翻译：分类系统包括从标签项目的键的软件管理树测试位。通过将选择位算法应用于规则数据库中的规则来选择位。包含逻辑的控制器在二叉树的决策节点中解析要测试的位的未知密钥。由树进行的测试以预定的方式进行，直到从数据库中除了一个规则之外的所有除了数据库中的所有规则或从数据库中除了少数几个规则之外的所有测试都被消除，由此Key被完整的一个规则或由剩余的多个规则，以确定对该项目执行的操作。在二叉树中使用某些比较测试，否则相同或相似的规则应用于不落在2边界的幂的关键值的整数范围。此外，这些最终测试中的一些非常频繁出现的规则可能被指定为次要规则，剩余的规则被指定为主要规则，仅使用主要规则重新计算的整个决策树，然后仅在逻辑上必要时连接到次级规则的主要规则使用指针的相对优先级的指针系统的手段。

10. 发明授权

US06463500B1 Apparatus and method to access computer memory by processing object data as sub-object and shape parameter 失效
公开(公告)号：US06463500B1
公开(公告)日：2002-10-08
申请号：US09477775
申请日：2000-01-04
申请人： Marco C. Heddes , Piyush Chunilal Patel , Mark Anthony Rinaldi
发明人： Marco C. Heddes , Piyush Chunilal Patel , Mark Anthony Rinaldi
IPC分类号： G06F1200
CPC分类号： G06F17/30607 , G06F12/0207 , G06F17/3061
摘要： A method is provided for utilizing a memory system which allows for the fast and efficient writing and reading of objects to and from diverse memory chips. A computer system and memory system complex according to method is also provided. The invention defines objects in terms of “shapes.” The shape of an object is defined by two parameters: “Width” and “Height.” Memory system memory chips may comprise sets of different kinds of memory modules which vary in terms of access speed, latency and memory width, such as for example DRAM or SRAM memory modules. The Height of an object denotes the number of consecutive address locations at which the object is stored on a memory module. The Width of an object denotes the number of memory modules at which the object is stored. An advantage of the invention is that objects are defined in terms of “sub-objects” optimized for the memory system memory modules. The sub-objects match the line-width of the memory, thereby allowing the objects to be efficiently written to different memories or memory banks. A further advantage of the invention is that the sub-object shape is transparent to the requester (i.e. transparent to application assembly language). A further advantage of the invention is that sub-objects are handled independently by the memory arbiter, i.e. they can be written to the memory or read from the memory in any order. The complex may further comprise a Tree Search Memory (TSM) system that utilizes a “tree” object hierarchy to perform high-speed memory lookups. Shaping is used to specify how an object is stored in the TSM. The trees consist of different kinds of objects with different shapes. An important advantage of the invention is that the concept of shapes can be used for memory bandwidth distribution and performance increase, allowing objects that are frequently read from memory to be distributed in specific sub-object ordering.

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