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1. 发明授权

US06769033B1 Network processor processing complex and methods 失效
标题翻译：网络处理器处理复杂和方法
公开(公告)号：US06769033B1
公开(公告)日：2004-07-27
申请号：US09384691
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F900
CPC分类号： H04L49/602 , G06F15/80 , H04L49/351
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过嵌入式处理器复合体与一组外围设备的协作来增强数据流处理和灵活性，这些外围设备都形成在公共半导体衬底上。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成于半导体衬底上的指令存储器中的指令的控制下操作，同时由存储器外围设备和与外部存储器元件的接口提供过渡数据流部分的存储。

2. 发明授权

US06588008B1 Assembler tool for processor-coprocessor computer systems 失效
标题翻译：处理器 - 协处理器计算机系统的汇编工具
公开(公告)号：US06588008B1
公开(公告)日：2003-07-01
申请号：US09546755
申请日：2000-04-11
申请人： Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F945
CPC分类号： G06F9/30043 , G06F8/47 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/3885
摘要： A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.
摘要翻译：一种中央处理器 - 协处理器组件，其包括用于将基本中央处理器任务扩展到至少一个协处理器的汇编器软件工具。重要的是，当对协处理器元素进行更改时，汇编程序软件工具不需要重新构建。本发明允许基本核心语言处理（CLP）编程模型的组装时间扩展，而不需要重建汇编器工具本身。汇编器工具包括使得中央处理器能够操纵协处理器寄存器的一组命令，以及协处理器执行指令，其在协处理器上启动命令处理。本发明通过使得硬件设计者能够更新其协处理器定义文件以反映新的或修改的协处理器，通过多个硬件修订来简化了汇编工具的维护。

3. 发明授权

US06829697B1 Multiple logical interfaces to a shared coprocessor resource 失效
标题翻译：到共享协处理器资源的多个逻辑接口
公开(公告)号：US06829697B1
公开(公告)日：2004-12-07
申请号：US09656582
申请日：2000-09-06
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F1500
CPC分类号： G06F15/7864
摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.
摘要翻译：嵌入式处理器复合体包含多个协议处理器单元（PPU）。每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。

4. 发明授权

US07093109B1 Network processor which makes thread execution control decisions based on latency event lengths 失效
标题翻译：基于延迟事件长度的线程执行控制决策的网络处理器
公开(公告)号：US07093109B1
公开(公告)日：2006-08-15
申请号：US09542189
申请日：2000-04-04
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802
摘要： A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.
摘要翻译：在网络处理器和树形搜索协处理器之间建立一种控制机制来处理访问诸如以树结构格式化的信息的数据的延迟。排队多个独立的指令执行线程使其能够快速访问共享存储器。如果由于延迟事件导致线程执行失败，则会对队列中的下一个线程授予完全控制权。当长时间延迟事件发生时，发生短延迟事件或满时，授权控制是暂时的。当短暂延迟事件完成时，控制返回到原始线程。每个执行线程使用指令预取缓冲器，当指令带宽未被活动执行线程充分利用时，该指令预取缓冲器收集空闲执行线程的指令。线程执行控制由FIFO，仲裁器和线程控制状态机的集合功能决定。

5. 发明授权

US06931641B1 Controller for multiple instruction thread processors 失效
标题翻译：多指令线程处理器的控制器
公开(公告)号：US06931641B1
公开(公告)日：2005-08-16
申请号：US09542206
申请日：2000-04-04
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48 , G06F9/52 , G06F15/16 , G06F9/00
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译：机构控制多线程处理器，使得当第一线程遇到延迟事件到第一预定义时间间隔时，临时控制在第一预定义时间间隔的持续时间内传送到备用执行线程，然后返回到原始线程。当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

6. 发明授权

US06785278B1 Methods, systems and computer program products for hashing address values 失效
标题翻译：用于散列地址值的方法，系统和计算机程序产品
公开(公告)号：US06785278B1
公开(公告)日：2004-08-31
申请号：US09210222
申请日：1998-12-10
申请人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Ross Boyd Leavens , Gerald Arnold Marin , Piyush Chunilal Patel , Atef Omar Zaghloul
发明人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Ross Boyd Leavens , Gerald Arnold Marin , Piyush Chunilal Patel , Atef Omar Zaghloul
IPC分类号： H04L1228
CPC分类号： H04L12/4625 , H04L45/745
摘要： Methods systems and computer program products are provided for hashing address values that exhibit banding in a plurality of regions of an address space defined by at least two segments of the address values, by performing at least one of a translation and a rotation of the at least two segments to thereby map the at least two segments from the plurality of regions to one of the plurality of regions.
摘要翻译：提供了方法系统和计算机程序产品，用于通过执行至少一个地址值的平移和旋转中的至少一个来散列地址值，所述地址值在由地址值的至少两个段定义的地址空间的多个区域中呈现带状从而将多个区域中的至少两个区段映射到多个区域中的一个区域。

7. 发明授权

US08006244B2 Controller for multiple instruction thread processors 失效
标题翻译：多指令线程处理器的控制器
公开(公告)号：US08006244B2
公开(公告)日：2011-08-23
申请号：US10915983
申请日：2004-08-11
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
IPC分类号： G06F9/46
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译：机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

8. 发明授权

US07440417B2 Method and system for frame and protocol classification 失效
标题翻译：框架和协议分类的方法和系统
公开(公告)号：US07440417B2
公开(公告)日：2008-10-21
申请号：US10870730
申请日：2004-06-17
申请人： Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel , Jean Louis Calvignac , Gordon Taylor Davis
发明人： Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel , Jean Louis Calvignac , Gordon Taylor Davis
IPC分类号： H04L12/28
CPC分类号： H04L29/06 , H04L69/18 , H04L69/22
摘要： A system and method of protocol and frame classification in a system for data processing is disclosed, including, analyzing a portion of the, packet or frame according to predetermined tests, and storing characteristics of the packet for use in subsequent processing of the frame. The characteristics are preferably obtained with hardware, which does so quickly and in a uniform time period. The stored characteristics of the packet are then used by the network processing complexes in further processing of the frame. The processor is preconditioned with a starting instruction address or cede entry point and the location of the beginning of the layer 3 header as well as flags for the type of frame.
摘要翻译：公开了一种用于数据处理的系统中的协议和帧分类的系统和方法，包括：根据预定的测试分析一部分数据包或帧，以及存储该数据包的特性以用于帧的后续处理。这些特征优选地通过硬件获得，硬件在快速且均匀的时间周期内这样做。然后，分组的存储特性由网络处理复合体用于帧的进一步处理。处理器使用开始指令地址或者入门点进行预处理，并且第3层头的开始位置以及帧类型的标志。

9. 发明授权

US06775284B1 Method and system for frame and protocol classification 失效
标题翻译：框架和协议分类的方法和系统
公开(公告)号：US06775284B1
公开(公告)日：2004-08-10
申请号：US09479027
申请日：2000-01-07
申请人： Jean Louis Calvignac , Gordon Taylor Davis , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel
发明人： Jean Louis Calvignac , Gordon Taylor Davis , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel
IPC分类号： H04L1256
CPC分类号： H04L29/06 , H04L69/18 , H04L69/22
摘要： A system and method of protocol and frame classification in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the packet or frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit, such as the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address and flags indicating whether the frame uses a virtual local area network, preferably using hardware to quickly and in a uniform time period. The stored key characteristics of the packet are then used by the network processing complexes in its further processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additionally, additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions.
摘要翻译：用于数据处理（例如，切换或路由数据分组或帧）的系统中的协议和帧分类的系统和方法。本发明包括根据预定的测试来分析分组或帧的一部分，然后存储该分组的关键特征以用于该帧的后续处理。帧（或输入信息单元，例如帧中使用的层3协议的类型，第2层封装技术，起始指令地址和指示帧是否使用虚拟局域网的标志）的关键特性，优选地使用硬件在快速和统一的时间段内，存储的密钥特性随后由网络处理复合体在帧的进一步处理中被使用，处理器使用起始指令地址和开始指令的位置进行预处理第3层标题以及帧类型的标志，即处理器使用指令地址或代码入口点，根据帧类型对正确位置的帧开始处理，另外附加指令地址可以在分支上顺序堆叠和使用，以避免额外的测试和分支指令。

10. 发明授权

US07107265B1 Software management tree implementation for a network processor 失效
标题翻译：网络处理器的软件管理树实现
公开(公告)号：US07107265B1
公开(公告)日：2006-09-12
申请号：US09545100
申请日：2000-04-06
申请人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi
发明人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi
IPC分类号： G06F17/30 , G06F15/00 , G06F9/44
CPC分类号： H04L45/742 , G06F17/30961 , G06F17/30985 , Y10S707/99933 , Y10S707/99936 , Y10S707/99937
摘要： Novel data structures, methods and apparatus for a Software Managed Tree (SMT) which provides a mechanism to create tree structures that follow a search mechanism defined by a control point processor. The search mechanism does not require storage on the previous pointer and uses only a forward pointer along with a next bit or group of bits to test thereby reducing storage space for nodes. The search mechanism processes multiple filter rules for an application without requiring multiple searches and also allows various filter rules to be chained. Two patterns of the same length are stored in each leaf to define a range compare. A compare at the end operation is either a compare under range or a compare under mask. In a compare under range, the input key is checked to determine if it is in the range defined by the two patterns. In a compare under mask, the bits in the input key are compared with the bits in a first leaf pattern under a mask specified in a second leaf pattern.
摘要翻译：用于软件管理树（SMT）的新型数据结构，方法和装置，其提供了一种机制，用于创建遵循由控制点处理器定义的搜索机制的树结构。搜索机制不需要在前一个指针上存储，并且仅使用前向指针以及下一个位或一组位来进行测试，从而减少节点的存储空间。搜索机制处理应用程序的多个过滤器规则，而不需要多次搜索，并且还允许链接各种过滤器规则。在每个叶中存储相同长度的两个图案以定义范围比较。在最终操作中的比较是在范围之下的比较或掩码下的比较。在范围比较范围内，检查输入键以确定是否在两种模式定义的范围内。在掩码下的比较中，将输入密钥中的比特与在第二叶图案中指定的掩码下的第一叶图案中的比特进行比较。

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