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1. 发明授权

US4450365A Digital logic buffer for converting single polarity analog signals to dual polarity analog signals 失效
标题翻译：用于将单极性模拟信号转换为双极性模拟信号的数字逻辑缓冲器
公开(公告)号：US4450365A
公开(公告)日：1984-05-22
申请号：US302318
申请日：1981-09-14
申请人： Marcian E. Hoff, Jr. , Marshall A. Townsend , Stephen F. Dreyer
发明人： Marcian E. Hoff, Jr. , Marshall A. Townsend , Stephen F. Dreyer
IPC分类号： G06F17/10 , H03K17/66 , H03K5/156
CPC分类号： G06F17/10
摘要： A digital logic buffer device for generating dual polarity analog signals is described. In the presently preferred embodiment, buffer receives the positive polarity analog output of a digital-to-analog converter (V.sub.DAC), and a sign bit. If the sign bit indicates that a positive polarity is required, the buffer will output approximately V.sub.DAC. If a negative polarity is required, aproximately -V.sub.DAC will be generated.
摘要翻译：描述用于产生双极性模拟信号的数字逻辑缓冲器件。在当前优选的实施例中，缓冲器接收数模转换器（VDAC）的正极性模拟输出和符号位。如果符号位表示需要正极性，则缓冲器将输出大约VDAC。如果需要负极性，则会产生近似的-VDAC。

2. 发明授权

US4319325A Digital processor for processing analog signals 失效
标题翻译：用于处理模拟信号的数字处理器
公开(公告)号：US4319325A
公开(公告)日：1982-03-09
申请号：US120701
申请日：1980-02-11
申请人： Marcian E. Hoff, Jr. , Marshall A. Townsend , Stephen F. Dreyer
发明人： Marcian E. Hoff, Jr. , Marshall A. Townsend , Stephen F. Dreyer
IPC分类号： G06F17/10 , G06F7/48 , G06F7/52
CPC分类号： G06F17/10
摘要： An integrated circuit processor real time processing of analog signals is described. The programmable processor duplicates filters, waveform generators and non-linear functions, such as rectification, with a high degree of stability and at a relatively low cost. A two-port, random-access memory provides inputs to an arithmetic logic unit (ALU). One of these inputs is coupled through a scaler (shifter). This scaler in conjunction with the ALU provides efficient multiplication, particularly by coefficients. ALU overflows are handled in an unusual manner to eliminate additional processing time for overflows. In a typical application, the one chip processor, with its 192-word program, samples an input analog signal at the rate of 13,020 Hz and detects the 8 tones used in telephony.
摘要翻译：描述了模拟信号的集成电路处理器实时处理。可编程处理器以高度的稳定性和相对较低的成本重复滤波器，波形发生器和非线性功能，例如整流。两端口随机存取存储器向算术逻辑单元（ALU）提供输入。这些输入之一通过缩放器（移位器）耦合。这种与ALU结合的缩放器提供了有效的乘法，特别是通过系数。 ALU溢出以不寻常的方式处理，以消除溢出的额外处理时间。在典型的应用中，单芯片处理器以其192个字节的程序对13,020 Hz的输入模拟信号进行采样，并检测电话中使用的8个音调。

3. 发明申请

US20100308739A1 Apparatus, Method and System for Providing AC Line Power to Lighting Devices 有权
标题翻译：为照明设备提供交流线路电源的设备，方法和系统
公开(公告)号：US20100308739A1
公开(公告)日：2010-12-09
申请号：US12478293
申请日：2009-06-04
申请人： Anatoly Shteynberg , Dongsheng Zhou , Harry Rodriguez , Mark Eason , Bradley M. Lehman , Stephen F. Dreyer , Thomas J. Riordan
发明人： Anatoly Shteynberg , Dongsheng Zhou , Harry Rodriguez , Mark Eason , Bradley M. Lehman , Stephen F. Dreyer , Thomas J. Riordan
IPC分类号： H05B37/00
CPC分类号： H05B33/083 , H05B33/0845 , H05B33/089
摘要： An apparatus, method and system are disclosed for providing AC line power to lighting devices such as light emitting diodes (“LEDs”). An exemplary apparatus comprises: a plurality of LEDs coupled in series to form a first plurality of segments of LEDs; a plurality of switches coupled to the plurality of segments of LEDs to switch a selected segment into or out of a series LED current path in response to a control signal; a memory; and a controller which, in response to a first parameter and during a first part of an AC voltage interval, determines and stores in the memory a value of a second parameter and generates a first control signal to switch a corresponding segment of LEDs into the series LED current path; and during a second part of the AC voltage interval, when a current value of the second parameter is substantially equal to the stored value, generates a second control signal to switch a corresponding segment of LEDs out of the first series LED current path.
摘要翻译：公开了一种用于向例如发光二极管（“LED”）等照明装置提供AC线电力的装置，方法和系统。示例性装置包括：串联耦合以形成LED的第一多个段的多个LED; 耦合到所述多个LED段的多个开关，以响应于控制信号将所选择的段切换到串联LED电流路径中或从串联LED电流路径中切换出; 记忆以及控制器，其响应于第一参数并且在AC电压间隔的第一部分期间确定并存储在存储器中的第二参数的值，并且生成第一控制信号，以将相应的LED段切换成系列 LED电流路径; 并且在所述交流电压间隔的第二部分期间，当所述第二参数的当前值基本上等于所述存储值时，产生第二控制信号以将相应的LED段切换出所述第一串联LED电流路径。

4. 发明授权

US06862714B2 Accurately tuning resistors 有权
标题翻译：精确调谐电阻
公开(公告)号：US06862714B2
公开(公告)日：2005-03-01
申请号：US10126402
申请日：2002-04-19
申请人： Robert X. Jin , Vivian Hu , Stephen F. Dreyer
发明人： Robert X. Jin , Vivian Hu , Stephen F. Dreyer
IPC分类号： H03H7/24 , G06F17/50 , G06F9/45 , H01P5/08 , H03H7/38
CPC分类号： H03H7/24
摘要： Resistors may be more accurately tuned by using an external resistor and comparing the value of an internal resistor to the value of the external resistor. The value of the internal resistor may be adjusted to match the value of the external resistor. Any number of on-chip resistors may then be matched and adjusted using the information obtained with respect to the first internal resistor.
摘要翻译：可以通过使用外部电阻器将内部电阻器的值与外部电阻器的值进行比较来更精确地调节电阻器。可以调整内部电阻的值以匹配外部电阻的值。然后可以使用相对于第一内部电阻器获得的信息来匹配和调整任何数量的片上电阻器。

5. 发明授权

US06173380B2 Apparatus and method for providing multiple channel clock-data alignment 失效
标题翻译：用于提供多通道时钟数据对准的装置和方法
公开(公告)号：US06173380B2
公开(公告)日：2001-01-09
申请号：US09118700
申请日：1998-07-16
申请人： Robert X. Jin , Eric T. West , Stephen F. Dreyer
发明人： Robert X. Jin , Eric T. West , Stephen F. Dreyer
IPC分类号： G06F1300
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0008
摘要： An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.
摘要翻译：提供了一种用于根据单个时钟对准任意数量的数据信号的多个并行通道的装置和方法。通过使用先入先出（FIFO）原理和为每个接收到的数据信道实现FIFO原理的各个存储元件来实现同步过程。每个通道的数据信号被读入对应的存储元件，按顺序保持，并且在与指定的单个时钟信号同步的断言读出信号时被读出。该装置和方法优选地使用准备从实现FIFO原理的存储元件读取的数据的指示和主时钟信号的存在，以激活从对应的存储元件读取数据。因此，每个数据通道与主时钟信号完全对齐。可以为100BASE-T4接收机实现时钟数据对准功能。

6. 发明授权

US5454008A Method and apparatus for interfacing between a twisted pair and an intelligent cell 失效
标题翻译：用于在双绞线和智能电池之间进行接口的方法和装置
公开(公告)号：US5454008A
公开(公告)日：1995-09-26
申请号：US303635
申请日：1994-09-09
申请人： Donald D. Baumann , W. Mike Berke , Stephen F. Dreyer , Rod G. Sinks , Kurt A. Stoll
发明人： Donald D. Baumann , W. Mike Berke , Stephen F. Dreyer , Rod G. Sinks , Kurt A. Stoll
IPC分类号： H04B3/36 , H04B3/50 , H04L5/14 , H04L12/28 , H04L25/02 , H04L25/20 , H04L25/49 , H04L5/24 , H04B1/38
CPC分类号： H04L25/20 , H04L25/02 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L5/1461 , H04L25/0264
摘要： A transceiver module for coupling between cells in a distributed intelligence network and a twisted pair line. The module receives power from the line and provides power to its respective cell. At the end of transmitting a packet, the transceiver transmits a code violation, then an anti-code violation to dissipate energy in the line. This is followed by clamping the line for the dead time between packets. N transceivers may be connected (without a cell) to form a repeater. The transceiver module may be used in a network having free topology; that is, an ideal transmission line, with terminators is not needed.
摘要翻译：用于耦合分布式智能网络中的单元和双绞线之间的收发模块。该模块从线路接收电力并向其相应的电池供电。在发送数据包结束时，收发器发送代码违规，然后发送反码违反以消散线路中的能量。之后，将线路夹在数据包之间的死区时间。可以连接N个收发器（没有单元）以形成中继器。收发器模块可以在具有自由拓扑的网络中使用; 也就是说，不需要带有终端器的理想传输线。

7. 发明授权

US08569956B2 Apparatus, method and system for providing AC line power to lighting devices 有权
标题翻译：用于向照明装置提供交流线路电力的装置，方法和系统
公开(公告)号：US08569956B2
公开(公告)日：2013-10-29
申请号：US13283201
申请日：2011-10-27
申请人： Anatoly Shteynberg , Dongsheng Zhou , Stephen F. Dreyer , Harlan Ohara , Sinan Doluca
发明人： Anatoly Shteynberg , Dongsheng Zhou , Stephen F. Dreyer , Harlan Ohara , Sinan Doluca
IPC分类号： H05B37/00 , H05B41/00
CPC分类号： H05B33/083 , H05B33/0809 , H05B33/0815 , H05B33/0827 , H05B33/0845 , H05B33/0857 , H05B33/089
摘要： An apparatus, method and system are disclosed for providing AC line power to lighting devices such as light emitting diodes (“LEDs”). A representative apparatus comprises: a plurality of LEDs coupled in series to form a plurality of segments of LEDs; first and second current regulators; a current sensor; and a controller to monitor a current level through a series LED current path, and to provide for first or second segments of LEDs to be in or out of the series LED current path at different current levels. A voltage regulator is also utilized to provide a voltage during a zero-crossing interval of the AC voltage. In a representative embodiment, first and second segments of LEDs are both in the series LED current path regulated at a lower current level compared to when only the first segment of LEDs is in the series LED current path.
摘要翻译：公开了一种用于向例如发光二极管（“LED”）等照明装置提供AC线电力的装置，方法和系统。代表性装置包括：串联耦合以形成多个LED段的多个LED; 第一和第二电流调节器; 电流传感器; 以及控制器，用于通过串联LED电流路径监视电流水平，并且提供LED的第一或第二段在不同电流水平下进入或流出串联LED电流路径。还利用电压调节器在交流电压的零交叉间隔期间提供电压。在代表性实施例中，与当仅第一LED段处于串联LED电流路径时相比，LED的第一和第二段都处于LED电流路径中调节在较低电流水平。

8. 发明授权

US06879187B2 Signal detect circuit for high speed data receivers 失效
标题翻译：用于高速数据接收机的信号检测电路
公开(公告)号：US06879187B2
公开(公告)日：2005-04-12
申请号：US10609802
申请日：2003-06-30
申请人： Robert X. Jin , Kathy L. Peng , Stephen F. Dreyer
发明人： Robert X. Jin , Kathy L. Peng , Stephen F. Dreyer
IPC分类号： G01R23/00 , H03K5/08 , H03K5/153 , H03K5/26 , H03K5/22
CPC分类号： G01R23/005 , H03K5/08 , H03K5/153 , H03K5/26
摘要： In accordance with one embodiment of the present invention, a signal detect circuit may analyze an input signal before passing it on to a receiver. The analysis may be done outside of the data path to avoid affecting the data path speed or adding distortion or jitter. The positive and negative thresholds of the data may be checked to see if the numbers of positive and negative crossings are comparable. Random and bursty noise can be detected since such noise normally does not have comparable positive and negative crossings.
摘要翻译：根据本发明的一个实施例，信号检测电路可以在输入信号传送到接收器之前分析输入信号。分析可以在数据路径之外进行，以避免影响数据路径速度或增加失真或抖动。可以检查数据的正和负阈值以查看正和负交叉的数量是否可比。可以检测到随机和突发噪声，因为这种噪声通常不具有可比的正负交叉。

9. 发明授权

US06614271B1 Signal detect circuit for high speed data receivers 失效
标题翻译：用于高速数据接收机的信号检测电路
公开(公告)号：US06614271B1
公开(公告)日：2003-09-02
申请号：US10171071
申请日：2002-06-13
申请人： Robert X. Jin , Kathy L. Peng , Stephen F. Dreyer
发明人： Robert X. Jin , Kathy L. Peng , Stephen F. Dreyer
IPC分类号： H03K5153
CPC分类号： G01R23/005 , H03K5/08 , H03K5/153 , H03K5/26
摘要： In accordance with one embodiment of the present invention, a signal detect circuit may analyze an input signal before passing it on to a receiver. The analysis may be done outside of the data path to avoid affecting the data path speed or adding distortion or jitter. The positive and negative thresholds of the data may be checked to see if the numbers of positive and negative crossings are comparable. Random and bursty noise can be detected since such noise normally does not have comparable positive and negative crossings.
摘要翻译：根据本发明的一个实施例，信号检测电路可以在输入信号传送到接收器之前分析输入信号。分析可以在数据路径之外进行，以避免影响数据路径速度或增加失真或抖动。可以检查数据的正和负阈值以查看正和负交叉的数量是否可比。可以检测到随机和突发噪声，因为这种噪声通常不具有可比的正负交叉。

10. 发明授权

US6011822A Differential charge pump based phase locked loop or delay locked loop 失效
标题翻译：基于差分电荷泵的锁相环或延迟锁定环
公开(公告)号：US6011822A
公开(公告)日：2000-01-04
申请号：US843936
申请日：1997-04-17
申请人： Stephen F. Dreyer
发明人： Stephen F. Dreyer
IPC分类号： H03K3/0231 , H03K3/03 , H03L7/081 , H03L7/089 , H03L7/099 , H03D3/24
CPC分类号： H03L7/0896 , H03K3/0231 , H03K3/03 , H03K3/0322 , H03L7/0812 , H03L7/0893 , H03L7/0995 , H03L2207/06
摘要： A phase locked loop includes a differential charge pump to cancel static phase error and reduce sensitivity to noise. The differential charge pump comprises two substantially identical single-ended charge pumps so that under locked condition, changes in voltage at the charge pumps' output terminals are substantially identical, thereby maintaining a substantially constant difference between the charge pumps' output voltage. A differential input voltage-controlled oscillator receives the output of the differential charge pump and generates a clock signal with a frequency proportional to the voltage difference output by the differential charge pump. A common mode bias circuit adjusts the common mode voltage output by the differential charge pump to optimize the voltage swing available at the differential charge pump's output terminals. The structure can be easily modified to implement a delay locked loop by replacing the differential input voltage-controlled oscillator with a differential input voltage-controlled delay circuit.
摘要翻译：锁相环包括一个差分电荷泵，以消除静态相位误差并降低对噪声的灵敏度。差分电荷泵包括两个基本上相同的单端电荷泵，使得在锁定状态下，电荷泵的输出端子处的电压变化基本相同，从而在电荷泵的输出电压之间保持基本恒定的差。差分输入压控振荡器接收差分电荷泵的输出，并产生与差分电荷泵输出的电压差成比例的频率的时钟信号。共模偏置电路调节由差分电荷泵输出的共模电压，以优化差分电荷泵输出端可用的电压摆幅。可以通过用差分输入电压控制延迟电路代替差分输入压控振荡器来轻松修改结构以实现延迟锁定环。

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