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1. 发明授权

US07529799B2 Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system 失效
标题翻译：分布式对称多处理器系统中交易标签分配和维护的方法和装置
公开(公告)号：US07529799B2
公开(公告)日：2009-05-05
申请号：US10162636
申请日：2002-06-05
申请人： Manuel Joseph Alvarez, II , Sanjay Raghunath Deshpande , Kenneth Douglas Klapproth , David Mui
发明人： Manuel Joseph Alvarez, II , Sanjay Raghunath Deshpande , Kenneth Douglas Klapproth , David Mui
IPC分类号： G06F15/16 , G06F15/167 , G06F15/173 , G06F17/30 , G06F13/28 , G06F9/34 , G06F12/00 , G06F21/00 , G06F13/00 , G06F9/26
CPC分类号： G06F12/0813 , Y10S707/99952
摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. A transaction tag format for a standard bus protocol is expanded to ensure unique transaction tags are maintained throughout the system. A sideband signal is used for intervention and Reruns to preserve transaction tags at the node controller in certain circumstances.
摘要翻译：提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。节点控制器从主设备接收事务，与主设备作为另一个主设备或从设备通信，并对从主设备接收的事务进行排队。由于一致性的实现在时间和空间上分布，所以节点控制器有助于维持高速缓存一致性。扩展标准总线协议的交易标签格式，以确保在整个系统中维护唯一的事务标签。在某些情况下，边带信号用于干预和重新分配，以在节点控制器上保留事务标签。

2. 发明授权

US06484220B1 Transfer of data between processors in a multi-processor system 有权
标题翻译：在多处理器系统中的处理器之间传输数据
公开(公告)号：US06484220B1
公开(公告)日：2002-11-19
申请号：US09383736
申请日：1999-08-26
申请人： Manuel Joseph Alvarez, II , Sanjay Raghunath Deshpande , Kenneth Douglas Klapproth , David Mui
发明人： Manuel Joseph Alvarez, II , Sanjay Raghunath Deshpande , Kenneth Douglas Klapproth , David Mui
IPC分类号： G06F302
CPC分类号： G06F15/17375 , G06F12/0831 , G06F13/4022
摘要： A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer system responds to the request and indicates the location of the device and whether the device contains the requested data. The data is then transferred to the requesting device from one of the devices containing the data within the plurality of devices to the requesting device. The device selected to transfer the data to the requesting device has the closest logical proximity to the requesting device which results in a quick transfer of data.
摘要翻译：一种用于在计算机系统中的设备之间传送数据的方法。在优选实施例中，请求设备广播数据请求。计算机系统内的多个设备中的每一个都响应该请求并且指示该设备的位置以及该设备是否包含所请求的数据。然后将数据从包含多个设备中的数据的设备之一传送到请求设备。被选择以将数据传送到请求设备的设备与请求设备的逻辑接近度最接近，这导致数据的快速传送。

3. 发明授权

US06510471B1 Method for choosing device among plurality of devices based on coherncy status of device's data and if device supports higher-performance transactions 失效
标题翻译：基于设备数据的切换状态选择设备的方法，以及设备如何支持更高性能的交易
公开(公告)号：US06510471B1
公开(公告)日：2003-01-21
申请号：US09392838
申请日：1999-09-09
申请人： Manuel Joseph Alvarez, II , Kenneth Douglas Klapproth , David Mui
发明人： Manuel Joseph Alvarez, II , Kenneth Douglas Klapproth , David Mui
IPC分类号： G06F1300
CPC分类号： G06F9/542
摘要： A method of transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data to other devices in the computer system. The computer system identifies, from a plurality of responding devices within the computer system, a target device that contains the data. In response to a determination that the target device does not support higher-performance transactions, the computer system disables higher-performance transactions and transfers the data to the requesting device via a lower-performance transaction process.
摘要翻译：一种在计算机系统中的设备之间传送数据的方法。在优选实施例中，请求设备向计算机系统中的其他设备广播对数据的请求。计算机系统从计算机系统内的多个响应设备识别包含数据的目标设备。响应于确定目标设备不支持更高性能的事务，计算机系统禁用更高性能的事务，并通过较低性能的事务处理将数据传送到请求设备。

4. 发明授权

US06449698B1 Method and system for bypass prefetch data path 失效
标题翻译：旁路预取数据路径的方法和系统
公开(公告)号：US06449698B1
公开(公告)日：2002-09-10
申请号：US09383743
申请日：1999-08-26
申请人： Sanjay Raghunath Deshpande , David Mui , Praveen S. Reddy
发明人： Sanjay Raghunath Deshpande , David Mui , Praveen S. Reddy
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/0888 , G06F2212/6022
摘要： A method and system for bypassing a prefetch data path is provided. Each transaction within a system is tagged, and as transactions are issued for retrieving data, the system has a data prefetch unit for prefetching data from a processor, a memory subsystem, or an I/O agent into a prefetch data buffer. A prefetch data buffer entry is allocated for a data prefetch transaction, and the data prefetch transaction is issued. While the prefetch transaction is pending, a read transaction is received from a transaction requestor. The address for the read transaction is compared with the addresses of the pending data prefetch transactions, and in response to an address match, the prefetch data buffer entry for the matching prefetch transaction is checked to determine whether data has been received for the data prefetch transaction. In response to a determination that data has not been received for the data prefetch transaction, the prefetch data buffer entry is deallocated, and the transaction tag for the data prefetch transaction is stored in a table for bypassing a prefetch data path. When data for a data prefetch transaction is received, its transaction tag is compared with transaction tags in the table for bypassing the prefetch data path, and in response to a transaction tag match, the received data is sent to the transaction requestor.
摘要翻译：提供了一种用于绕过预取数据路径的方法和系统。系统内的每个事务被标记，并且当发出用于检索数据的事务时，系统具有用于将数据从处理器，存储器子系统或I / O代理预取到预取数据缓冲器中的数据预取单元。为数据预取事务分配预取数据缓冲区条目，并发出数据预取事务。在预取事务处于待处理状态的同时，从事务请求者接收到读取事务。将读取事务的地址与待处理的数据预取事务的地址进行比较，并且响应于地址匹配，检查用于匹配预取事务的预取数据缓冲器条目以确定是否已经为数据预取事务接收了数据。响应于对数据预取事务尚未接收到数据的确定，取消预取数据缓冲器条目，并且用于数据预取事务的事务标签存储在用于绕过预取数据路径的表中。当接收到用于数据预取事务的数据时，其交易标签与表中的交易标签进行比较，以绕过预取数据路径，并且响应于事务标签匹配，所接收的数据被发送到事务请求者。

5. 发明授权

US06317811B1 Method and system for reissuing load requests in a multi-stream prefetch design 有权
标题翻译：在多流预取设计中重新发出加载请求的方法和系统
公开(公告)号：US06317811B1
公开(公告)日：2001-11-13
申请号：US09383737
申请日：1999-08-26
申请人： Sanjay Raghunath Deshpande , David Mui
发明人： Sanjay Raghunath Deshpande , David Mui
IPC分类号： G06F1208
CPC分类号： G06F9/345 , G06F9/383 , G06F12/0862 , G06F2212/6028
摘要： A method and system for reissuing load requests in a multi-stream prefetch engine of a data processing system is provided. A read transaction is received from a transaction requester, and the read transaction has a base address and a prefetch stream identifier. The received read transaction is issued to a prefetch stream associated with a data prefetch buffer identified by the prefetch stream identifier as the prefetch stream is one of a set of prefetch streams, each of which has an associated prefetch buffer. The read transaction is issued to a prefetch stream associated with a data prefetch buffer, and a set of prefetch addresses are generated, each prefetch address in the set of prefetch addresses being proximate to the base address. A determination is made as to whether the data prefetch buffer has unallocated prefetch buffer entries, and a comparison is made between each prefetch address in the set of prefetch addresses and all prefetch addresses in each data prefetch buffer to determine whether a prefetch address in the set of prefetch addresses collides with a prefetch address in a data prefetch buffer. In response to a determination of an absence of an address collision and a determination that the data prefetch buffer does not have an unallocated prefetch buffer entry, the base address is held for data prefetch reissuance.
摘要翻译：提供了一种用于在数据处理系统的多流预取引擎中重新发出加载请求的方法和系统。从交易请求者接收到读取事务，读取事务具有基地址和预取流标识符。接收到的读取事务被发布到与由预取流标识符标识的数据预取缓冲器相关联的预取流，因为预取流是一组预取流中的一个，每个预取流具有相关联的预取缓冲器。读取事务被发送到与数据预取缓冲器相关联的预取流，并且生成一组预取地址，预取地址集合中的每个预取地址靠近基地址。确定数据预取缓冲器是否具有未分配的预取缓冲器条目，并且在每个预取地址组中的每个预取地址和每个数据预取缓冲器中的所有预取地址之间进行比较，以确定该组中的预取地址预取地址与数据预取缓冲区中的预取地址相冲突。响应于确定没有地址冲突和确定数据预取缓冲器不具有未分配的预取缓冲器条目，保持基址用于数据预取重新发布。

6. 发明授权

US6134684A Method and system for error detection in test units utilizing pseudo-random data 失效
标题翻译：使用伪随机数据的测试单元中的错误检测方法和系统
公开(公告)号：US6134684A
公开(公告)日：2000-10-17
申请号：US30972
申请日：1998-02-25
申请人： Jason Raymond Baumgartner , Kenneth Douglas Klapproth , David Mui
发明人： Jason Raymond Baumgartner , Kenneth Douglas Klapproth , David Mui
IPC分类号： G06F11/267 , G01R31/28
CPC分类号： G06F11/2215 , G01R31/318385 , G06F11/221
摘要： A method and system in an integrated circuit for the detection of defects within integrated circuits and planars are disclosed. Initially, pseudo-random data is generated. Thereafter, the pseudo-random data is transferred to a bus interface unit that determines, based upon the pseudo-random data, a particular transaction that may be injected upon a test unit by the bus interface unit. Expected results of all types of transactions that may be injected upon the test unit are predetermined. The particular transaction is then injected upon the test unit. Such transactions can include transactions such as a bus store or bus load. The results of the particular transaction upon the test unit are then compared with the expected results, wherein a mismatch between the expected results and the results of the particular transaction upon the test unit exposes an error within the test unit, such that a variety of test units may be portably tested for errors without the need for preconfiguring the test units for testing.
摘要翻译：公开了一种用于检测集成电路和平面图中的缺陷的集成电路中的方法和系统。最初，生成伪随机数据。此后，伪随机数据被传送到总线接口单元，总线接口单元基于伪随机数据，确定由总线接口单元可以注入到测试单元上的特定事务。可能注入到测试单元上的所有类型的交易的预期结果是预先确定的。然后将特定事务注入到测试单元上。这种交易可以包括诸如总线存储或总线负载的事务。然后将测试单元上的特定交易的结果与预期结果进行比较，其中预期结果与测试单元上的特定交易的结果之间的不匹配暴露了测试单元内的错误，使得各种测试可以对单元进行可移动测试，而不需要预先配置测试单元进行测试。

7. 发明申请

US20110246695A1 CONTROLLING BANDWIDTH RESERVATIONS METHOD AND APPARATUS 失效
标题翻译：控制带宽预留方法和装置
公开(公告)号：US20110246695A1
公开(公告)日：2011-10-06
申请号：US13162917
申请日：2011-06-17
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： G06F12/00
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译：公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。任何非托管命令或数据包都按常规技术处理。

8. 发明授权

US07900027B2 Scalable link stack control method with full support for speculative operations 失效
标题翻译：可扩展的链路栈控制方法，完全支持投机操作
公开(公告)号：US07900027B2
公开(公告)日：2011-03-01
申请号：US12023913
申请日：2008-01-31
申请人： Ronald P. Hall , Michael Lance Karm , David Mui , Albert James Van Norstrand, Jr.
发明人： Ronald P. Hall , Michael Lance Karm , David Mui , Albert James Van Norstrand, Jr.
IPC分类号： G06F9/40 , G06F9/312
CPC分类号： G06F9/30134 , G06F9/30054 , G06F9/3806 , G06F9/3842
摘要： A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.
摘要翻译：计算机实现的方法，处理器芯片，计算机程序产品和管理链路栈的数据处理系统。数据处理系统利用推测性推送并从链路堆栈弹出。链路栈包括一组条目，并且每个条目包括一组状态位。第一指令的推测推送被接收到数据堆栈上，并且第一指令被存储到该组条目的第一条目中。第一位被设置为指示第一条指令是有效指令。第二位被设置为指示第一条指令被推测地推到链路栈上。更新链接堆栈指针控件以指示第一个条目是顶部数据堆栈条目。

9. 发明申请

US20100120647A1 COMPOSITION OF A CLEANING MATERIAL FOR PARTICLE REMOVAL 有权
标题翻译：用于颗粒去除的清洁材料的组成
公开(公告)号：US20100120647A1
公开(公告)日：2010-05-13
申请号：US12267345
申请日：2008-11-07
申请人： Ji Zhu , Arjun Mendiratta , David Mui
发明人： Ji Zhu , Arjun Mendiratta , David Mui
IPC分类号： C11D3/37
CPC分类号： C11D7/5004 , C11D3/222 , C11D3/3765 , C11D3/3773 , C11D3/3776
摘要： The embodiments of the present invention provide improved materials for cleaning patterned substrates with fine features. The cleaning materials have advantages in cleaning patterned substrates with fine features without substantially damaging the features. The cleaning materials are fluid, either in liquid phase, or in liquid/gas phase, and deform around device features; therefore, the cleaning materials do not substantially damage the device features or reduce damage all together. To assist removing of particles from the wafer (or substrate) surfaces, the polymeric compound of the polymers can contain a polar functional group, which can establish polar-polar molecular interaction and hydrogen bonds with hydrolyzed particles on the wafer surface. The polymers of a polymeric compound(s) with a large molecular weight form long polymer chains and network. The long polymer chains and/or polymer network show superior capabilities of capturing and entrapping contaminants, in comparison to conventional cleaning materials. The polymeric compound(s) of the polymers may also include a functional group that carries charge in the cleaning solution. The charge of the functional group of the polymers improves the particle removal efficiency.
摘要翻译：本发明的实施例提供用于清洁具有精细特征的图案化衬底的改进材料。清洁材料在清洁具有精细特征的图案化基材上具有优点，而基本上不损坏特征。清洁材料是流体，液相或液相/气相，并围绕装置特征变形; 因此，清洁材料基本上不会损坏设备特征或将损坏降低在一起。为了帮助从晶片（或衬底）表面去除颗粒，聚合物的聚合物可以含有极性官能团，其可以与晶片表面上的水解颗粒建立极性极性的分子相互作用和氢键。具有大分子量的高分子化合物的聚合物形成长的聚合物链和网络。与传统清洁材料相比，长的聚合物链和/或聚合物网络显示出捕获和捕获污染物的优异性能。聚合物的聚合物还可以包括在清洁溶液中携带电荷的官能团。聚合物官能团的电荷提高了颗粒去除效率。

10. 发明授权

US07203811B2 Non-fenced list DMA command mechanism 有权
标题翻译：非围栏列表DMA命令机制
公开(公告)号：US07203811B2
公开(公告)日：2007-04-10
申请号：US10631542
申请日：2003-07-31
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G00F13/28
CPC分类号： G06F13/28
摘要： A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.
摘要翻译：提供了一种用于处理计算机系统中的列表DMA命令的方法和装置。列表DMA命令涉及系统存储器的有效地址（EA）。系统中至少有一个处理器具有本地存储。列表DMA命令在DMA队列（DMAQ）中排队。列表元素从本地存储器获取到DMAQ。从DMAQ读取列表DMA命令。为列表元素发出总线请求。如果总线请求是最后一个请求，则确定当前列表元素是否是最后一个列表元素。如果当前列表元素不是最后的列表元素，则确定当前列表元素是否被围栏。如果当前列表元素没有围栏，则无论所有未完成的请求是否完成，都会获取下一个列表元素。

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