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1. 发明申请

US20080182335A1 DETECTION AND CHARACTERIZATION OF SiCOH-BASED DIELECTRIC MATERIALS DURING DEVICE FABRICATION 失效
标题翻译：器件制造过程中SiCOH基介电材料的检测与表征
公开(公告)号：US20080182335A1
公开(公告)日：2008-07-31
申请号：US11626975
申请日：2007-01-25
申请人： Manoj Balachandran , James A. Hagan , Ben Kim , Deoram Persaud , Adam D. Ticknor , Wei-Tsu Tseng
发明人： Manoj Balachandran , James A. Hagan , Ben Kim , Deoram Persaud , Adam D. Ticknor , Wei-Tsu Tseng
IPC分类号： H01L21/66 , B24B3/00
CPC分类号： B24B57/02 , B24B37/04
摘要： Processes and apparatuses are disclosed for detecting and characterizing SiCOH-based dielectric materials during integrated circuit fabrication. The processes generally include chromatographically analyzing a fluid stream generated during a process employed for device fabrication, e.g., during a wet strip, a chemical mechanical planarization process and the like.
摘要翻译：公开了用于在集成电路制造期间检测和表征SiCOH基介电材料的方法和装置。这些方法通常包括色谱分析在用于器件制造的工艺中产生的流体流，例如在湿条，化学机械平面化工艺等期间。

2. 发明申请

US20070190788A1 WAFER REMOVING FORCE REDUCTION ON CMP TOOL 审中-公开
标题翻译：在CMP工具上减少减少的浪费
公开(公告)号：US20070190788A1
公开(公告)日：2007-08-16
申请号：US11276137
申请日：2006-02-15
申请人： Manoj Balachandran , James Hagan , Ben Kim , Deoram Persaud , Adam Ticknor , Wei-Tsu Tseng
发明人： Manoj Balachandran , James Hagan , Ben Kim , Deoram Persaud , Adam Ticknor , Wei-Tsu Tseng
IPC分类号： H01L21/302 , H01L21/461 , H01L21/311
CPC分类号： H01L21/02024 , B24B37/345
摘要： Reduction of a wafer removing force on a chemical mechanical planarization (CMP) tool that includes planarizing a wafer on a platen at a wafer/platen interface; applying carbonated water to the wafer/platen interface so as to reduce the removing force; and removing the wafer from the platen.
摘要翻译：在化学机械平面化（CMP）工具上减少晶片去除力，其包括在晶片/压板界面处平台化压板上的晶片; 将碳酸水施加到晶片/压板界面，以减少去除力; 并从压板上移除晶片。

3. 发明授权

US08324622B2 Method of repairing probe pads 有权
标题翻译：修复探针垫的方法
公开(公告)号：US08324622B2
公开(公告)日：2012-12-04
申请号：US12651332
申请日：2009-12-31
申请人： John H. Zhang , Laertis Economikos , Robin Van Den Nieuwenhuizen , Wei-Tsu Tseng
发明人： John H. Zhang , Laertis Economikos , Robin Van Den Nieuwenhuizen , Wei-Tsu Tseng
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L22/20 , H01L22/14 , H01L24/05 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.
摘要翻译：一种方法，其包括在衬底上形成第一电平的有源电路，形成电连接到所述第一电平有源电路的第一探针焊盘，其中所述第一探针焊盘具有第一表面，所述第一探针焊盘与所述第一探针焊盘接触，所述第一探针焊盘的位于所述第一表面上方的部分，以及在所述第一探针焊盘上执行化学机械抛光，以在所述第一表面上方平坦化所述第一探针焊盘的所述部分。该方法还包括形成覆盖在第一探针焊盘上的第二电平有源电路，形成电连接到第二电平有源电路的第二探针焊盘，使第二探针焊盘与移位探针焊盘的一部分的探针尖接触，以及化学机械地抛光第二探针垫以除去所移动的部分。

4. 发明申请

US20050023689A1 Chemical planarization performance for copper/low-k interconnect structures 有权
标题翻译：铜/低k互连结构的化学平面化性能
公开(公告)号：US20050023689A1
公开(公告)日：2005-02-03
申请号：US10628925
申请日：2003-07-28
申请人： Lee Nicholson , Wei-Tsu Tseng , Christy Tyberg
发明人： Lee Nicholson , Wei-Tsu Tseng , Christy Tyberg
IPC分类号： H01L21/283 , H01L21/304 , H01L21/31 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5329 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/7684 , H01L21/7688 , H01L2924/0002 , Y10T428/31663 , H01L2924/00
摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.
摘要翻译：在基板上的电互连结构，其包括：第一低k电介质层; 共价键合到第一低k电介质层的自旋低k CMP保护层; 并提供CVD沉积的硬掩模/ CMP抛光停止层。可以在第一低k电介质层中形成电通孔和线。旋转低k CMP保护层可防止由于中心到边缘或不同金属密度区域的CMP工艺中的不均匀性而导致的低k电介质的损坏。可以调节低k CMP保护层的厚度以适应CMP工艺中的较大变化，而不显着影响结构的有效介电常数。

5. 发明授权

US06660820B1 Low dielectric constant polymer and monomers used in their formation 有权
标题翻译：低介电常数聚合物和用于其形成的单体
公开(公告)号：US06660820B1
公开(公告)日：2003-12-09
申请号：US10205278
申请日：2002-07-24
申请人： Arthur Martin , Wei-Tsu Tseng
发明人： Arthur Martin , Wei-Tsu Tseng
IPC分类号： C08F13616
CPC分类号： C08F36/20 , C08F38/00
摘要： A new class of fluorinated arylacetylene compounds useful as monomers in the formation of polymers having low dielectric constant. These polymers, which are the reaction products of one of the fluorinated arylacetylene compounds, a diphenyl oxide biscyclopentadienone and, optionally, 1,3,5-tris(phenylacetylene)benzene, are useful in insulating microelectric device.
摘要翻译：一类新的氟代芳基乙炔化合物，可用作形成具有低介电常数的聚合物的单体。这些聚合物是氟化芳基乙炔化合物之一，二苯基氧基双环戊二烯酮和任选的1,3,5-三（苯基乙炔）苯的反应产物，可用于绝缘微电子器件。

6. 发明授权

US06441465B2 Scribe line structure for preventing from damages thereof induced during fabrication 有权
标题翻译：用于防止在制造过程中引起的损坏的划痕线结构
公开(公告)号：US06441465B2
公开(公告)日：2002-08-27
申请号：US09246924
申请日：1999-02-09
申请人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
发明人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
IPC分类号： H01L23544
CPC分类号： H01L22/32 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture. Thereby, peeling, delamination and dielectric fracture of the scribe lines induced during the wafer manufacture can be prevented.
摘要翻译：在本发明中提供半导体晶片的划线结构。半导体晶片具有多个基本上平行的水平划线和多个基本上平行的垂直划线以将多个芯片彼此分开。根据本发明，每个平行的水平划线和每个平行的垂直划线沿其两个细长边划分成具有相同矩形区域的多个部分。每个划线的多个部分中的每一个由划线结构组成。划线结构包括多层结构，在每个划线的每个部分的整个区域上形成四边，并且沿多层结构的四边形成至少两排空腔。划痕线结构的空腔能够减轻划痕线的内部应力，并阻止在划线生产过程中引起的可能的裂纹。由此，能够防止在晶片制造时引起的划线的剥离，分层和介电断裂。

7. 发明授权

US06235608B1 STI process by method of in-situ multilayer dielectric deposition 有权
标题翻译： STI工艺采用原位多层电介质沉积法
公开(公告)号：US06235608B1
公开(公告)日：2001-05-22
申请号：US09292772
申请日：1999-04-14
申请人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
发明人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
IPC分类号： H01L21336
CPC分类号： H01L21/31144 , H01L21/31053 , H01L21/31612 , H01L21/3185 , H01L21/76224 , Y10S438/97
摘要： A process for forming shallow trench isolation (STI) structures. It includes the steps of: (a) depositing a composite silicon nitride on to the silicon substrate; (b) forming a shallow trench on the silicon substrate by etching, using the composite silicon nitride as the hard mask; (c) depositing a filler oxide layer inside the shallow trench as well as on top of the composite silicon nitride, using a chemical vapor deposition (CVD) method; and (d) using a chemical-mechanical polishing (CMP) process to planarize the filler oxide layer using the composite nitride as a CMP stop. The composite silicon nitride comprises a plurality of silicon nitride layers whose CMP removal rate increases with the distance from the silicon substrate. Additionally, a composite silicon oxide layer can be formed on top of the filler oxide layer which comprises a plurality of silicon oxide layers whose CMP removal rate increases with the distance from the silicon substrate.
摘要翻译：一种用于形成浅沟槽隔离（STI）结构的工艺。它包括以下步骤：（a）将复合氮化硅沉积到硅衬底上; （b）使用复合氮化硅作为硬掩模，通过蚀刻在硅衬底上形成浅沟槽; （c）使用化学气相沉积（CVD）方法在浅沟槽内以及在复合氮化硅的顶部上沉积填充氧化物层; 和（d）使用化学机械抛光（CMP）工艺来使用复合氮化物作为CMP停止层来平坦化填充氧化物层。复合氮化硅包括多个氮化硅层，其CMP去除率随着与硅衬底的距离而增加。此外，可以在填充氧化物层的顶部上形成复合氧化硅层，其包括多个氧化硅层，其CMP去除速率随着与硅衬底的距离而增加。

8. 发明授权

US07407879B2 Chemical planarization performance for copper/low-k interconnect structures 有权
标题翻译：铜/低k互连结构的化学平面化性能
公开(公告)号：US07407879B2
公开(公告)日：2008-08-05
申请号：US11369476
申请日：2006-03-07
申请人： Lee M Nicholson , Wei-Tsu Tseng , Christy S Tyberg
发明人： Lee M Nicholson , Wei-Tsu Tseng , Christy S Tyberg
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/7684 , H01L21/7688 , H01L2924/0002 , Y10T428/31663 , H01L2924/00
摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.
摘要翻译：在基板上的电互连结构，其包括：第一低k电介质层; 共价键合到第一低k电介质层的自旋低k CMP保护层; 并提供CVD沉积的硬掩模/ CMP抛光停止层。可以在第一低k电介质层中形成电通孔和线。旋转低k CMP保护层可防止由于中心到边缘或不同金属密度区域的CMP工艺中的不均匀性而导致的低k电介质的损坏。可以调节低k CMP保护层的厚度以适应CMP工艺中的较大变化，而不显着影响结构的有效介电常数。

9. 发明授权

US07071539B2 Chemical planarization performance for copper/low-k interconnect structures 有权
公开(公告)号：US07071539B2
公开(公告)日：2006-07-04
申请号：US10628925
申请日：2003-07-28
申请人： Lee M Nicholson , Wei-Tsu Tseng , Christy S Tyberg
发明人： Lee M Nicholson , Wei-Tsu Tseng , Christy S Tyberg
IPC分类号： H01L23/58 , H01L23/48
CPC分类号： H01L23/5329 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/7684 , H01L21/7688 , H01L2924/0002 , Y10T428/31663 , H01L2924/00
摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

10. 发明授权

US07008871B2 Selective capping of copper wiring 有权
标题翻译：铜线选择性封盖
公开(公告)号：US07008871B2
公开(公告)日：2006-03-07
申请号：US10611931
申请日：2003-07-03
申请人： Panayotis C. Andricacos , Shyng-Tsong Chen , John M. Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe M. Vereecken
发明人： Panayotis C. Andricacos , Shyng-Tsong Chen , John M. Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe M. Vereecken
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/6708 , H01L21/76849 , H01L21/7685 , H01L21/76874 , H01L21/76883
摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
摘要翻译：通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

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