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1. 发明授权

US06477447B1 Methods to generate numerical pressure distribution data for developing pressure related components 失效
标题翻译：生成压力分布数据的方法用于开发压力相关组件
公开(公告)号：US06477447B1
公开(公告)日：2002-11-05
申请号：US09417866
申请日：1999-10-13
申请人： Chi-Fa Lin
发明人： Chi-Fa Lin
IPC分类号： G05D1500
CPC分类号： B24B37/04 , B24B49/16 , H01L21/30625
摘要： A method of detecting surface pressure distribution of a wafer being processed by a CMP (Chemical Mechanical Polishing) process; more specifically, the invention relates to a method of detecting pressure distribution of a wafer surface by employing pressure sensitive films located on various pressure components such as a wafer carrier, a polishing pad, and mechanical arm members of a CMP machine for detecting pressure-related data during different stages of a CMP process. Further, sensed pressure-related data are collected for feedback loop controls of digital image mapping, numeration, simulation, and forecasting, from which more mechanical components of high precision and better circuit layouts on the wafer can then be developed.
摘要翻译：一种检测通过CMP（化学机械抛光）工艺处理的晶片的表面压力分布的方法; 更具体地，本发明涉及一种通过使用位于各种压力部件上的压敏膜（例如晶片载体，抛光垫和用于检测压力相关的CMP的机械臂部件）来检测晶片表面的压力分布的方法数据在CMP过程的不同阶段。此外，收集感测的压力相关数据用于数字图像映射，计数，模拟和预测的反馈环控制，从而可以开发更多的高精度和更好的电路布局的机械组件。

2. 发明授权

US06307268B1 Suppression of interconnect stress migration by refractory metal plug 有权
$Suppression of interconnect stress migration by refractory metal plug$
标题翻译：通过耐火金属插塞抑制互连应力迁移
公开(公告)号：US06307268B1
公开(公告)日：2001-10-23
申请号：US09476431
申请日：1999-12-30
申请人： Chi-Fa Lin
发明人： Chi-Fa Lin
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L23/53257 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for use in semiconductor devices, comprising: (a) a thin and elongated aluminum wire connected to a first metal structure; and (b) a plurality of regularly spaced dummy tungsten plugs which are connected to the aluminum wire at one end and are buried in an underlying dielectric layer so that it is insulated at the other end. The dummy tungsten plugs absorb the mobile aluminum atoms generated through stress-induced migration when the interconnect structure is subject to a rapid temperature change, thus preventing the via bulging problem which could seriously damage the second metal structure above the first metal structure.
摘要翻译：一种用于半导体器件的互连结构，包括：（a）连接到第一金属结构的薄而细长的铝线; 和（b）多个规则间隔的假钨塞，其在一端连接到铝线，并被埋在下面的电介质层中，使得在另一端绝缘。当互连结构经受快速温度变化时，假钨塞吸收通过应力诱导迁移产生的可移动铝原子，从而防止可能严重损坏第一金属结构之上的第二金属结构的通孔凸出问题。

3. 发明授权

US06180997B2 Structure for a multi-layered dielectric layer and manufacturing method thereof 失效
标题翻译：多层电介质层的结构及其制造方法
公开(公告)号：US06180997B2
公开(公告)日：2001-01-30
申请号：US09354024
申请日：1999-07-15
申请人： Chi-Fa Lin
发明人： Chi-Fa Lin
IPC分类号： H01L2358
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method and a structure of a multi-layered dielectric layer for forming openings in the dielectric layers for improving integration of integrated circuits, capability of step coverage, and problems caused by a structure of overhang, in which oblique sidewalls of the openings in multi-layered dielectric layer can improve the step coverage in the following manufacturing process.
摘要翻译：用于形成电介质层的开口的多层电介质层的制造方法和结构，用于提高集成电路的一体化，阶梯覆盖的能力以及由悬垂结构引起的问题，其中多孔开口的倾斜侧壁层状电介质层可以在以下制造过程中改善步骤覆盖。

4. 发明授权

US6165886A Advanced IC bonding pad design for preventing stress induced passivation cracking and pad delimitation through stress bumper pattern and dielectric pin-on effect 有权
标题翻译：先进的IC焊盘设计，用于通过应力保险杠图案和介电引脚效应防止应力诱发的钝化裂纹和焊盘定界
公开(公告)号：US6165886A
公开(公告)日：2000-12-26
申请号：US193298
申请日：1998-11-17
申请人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
发明人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
IPC分类号： H01L21/60 , H01L23/485 , H01L21/44
CPC分类号： H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48724 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： An improved metal bonding pad is disclosed which can prevent the formation of cracks during the high temperature PECVD deposition, and the subsequent annealing, of a passivation layer which is formed to encroach the metal bonding pad and provide an encapsulation force on the metal bonding pad. The metal bonding pad comprises a plurality of stress bumpers on the periphery thereof. The stress bumpers can be hollow elongated round-cornered rectangles, pin-shaped circles, Y-shaped polygons, or ellipses. The stress bumpers, which create a discontinuous structure in the metal pad, can effectively stop stress propagation as well as relieve and re-direct stress propagation, so as to maintain the integrity of the passivation encroachment and prevent the peeling off problems often observed with the metal bonding pad.
摘要翻译：公开了一种改进的金属焊盘，其可以防止在高温PECVD沉积期间形成裂纹，以及随后退火形成为钝化金属焊盘并在金属焊盘上提供封装力的钝化层。金属焊盘包括在其周边上的多个应力缓冲器。应力缓冲器可以是中空的长圆形矩形矩形，销状圆形，Y形多边形或椭圆形。在金属垫中产生不连续结构的应力缓冲器可以有效地阻止应力传播以及缓解并重新引导应力传播，从而保持钝化侵入的完整性，并防止剥离常见于金属焊盘。

5. 发明授权

US06033987A Method for mapping and adjusting pressure distribution of CMP processes 有权
标题翻译： CMP过程压力分布映射和调整方法
公开(公告)号：US06033987A
公开(公告)日：2000-03-07
申请号：US232179
申请日：1999-01-15
申请人： Chi-Fa Lin , Wen-Tsu Tseng , Min-Shinn Feng
发明人： Chi-Fa Lin , Wen-Tsu Tseng , Min-Shinn Feng
IPC分类号： B24B37/04 , B24B49/16 , H01L21/306 , H01L21/302
CPC分类号： B24B49/16 , B24B37/04 , B24B37/042
摘要： A method for chemically-and-mechanically polishing a semiconductor wafer surface is disclosed. It includes the steps of: (a) providing a mechanical polishing pad; (b) placing a pressure-sensitive film on top of a wafer surface to be polished by the mechanical polishing pad, the pressure-sensitive film contains materials that will show pressure-dependent colors when subject to an external pressure; (c) commencing a chemically-and-mechanically polishing process so that the mechanical polishing pad exerts a pressure on the pressure-sensitive film; (d) scanning the pressure-dependent color pattern on the pressure-sensitive film; (e) converting the pressure-dependent color pattern into a pressure distribution; and (f) adjusting the mechanical polishing pad, or a leveling of the wafer mounting, or both, according to the pressure distribution obtained in step (e).
摘要翻译：公开了一种用于化学和机械抛光半导体晶片表面的方法。它包括以下步骤：（a）提供机械抛光垫; （b）通过机械抛光垫将压敏胶片置于要抛光的晶片表面的顶部，压敏胶片含有当受到外部压力时会显示压力依赖性颜色的材料; （c）开始化学和机械抛光工艺，使得机械抛光垫对压敏膜施加压力; （d）扫描压敏胶片上的依赖于压力的色彩图案; （e）将压力依赖的颜色图案转换成压力分布; 和（f）根据步骤（e）中获得的压力分布来调整机械抛光垫，或者晶片安装的调平或两者。

6. 发明授权

US06441465B2 Scribe line structure for preventing from damages thereof induced during fabrication 有权
标题翻译：用于防止在制造过程中引起的损坏的划痕线结构
公开(公告)号：US06441465B2
公开(公告)日：2002-08-27
申请号：US09246924
申请日：1999-02-09
申请人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
发明人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
IPC分类号： H01L23544
CPC分类号： H01L22/32 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture. Thereby, peeling, delamination and dielectric fracture of the scribe lines induced during the wafer manufacture can be prevented.
摘要翻译：在本发明中提供半导体晶片的划线结构。半导体晶片具有多个基本上平行的水平划线和多个基本上平行的垂直划线以将多个芯片彼此分开。根据本发明，每个平行的水平划线和每个平行的垂直划线沿其两个细长边划分成具有相同矩形区域的多个部分。每个划线的多个部分中的每一个由划线结构组成。划线结构包括多层结构，在每个划线的每个部分的整个区域上形成四边，并且沿多层结构的四边形成至少两排空腔。划痕线结构的空腔能够减轻划痕线的内部应力，并阻止在划线生产过程中引起的可能的裂纹。由此，能够防止在晶片制造时引起的划线的剥离，分层和介电断裂。

7. 发明授权

US06323122B2 Structure for a multi-layered dielectric layer and manufacturing method thereof 失效
标题翻译：多层电介质层的结构及其制造方法
公开(公告)号：US06323122B2
公开(公告)日：2001-11-27
申请号：US09178464
申请日：1998-10-23
申请人： Chi-Fa Lin
发明人： Chi-Fa Lin
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method and a structure of a multi-layered dielectric layer for forming openings in the direction layers for improving integration of integrated circuits, capability of step coverage, and problems caused by a structure of overhang, in which oblique sidewalls of the openings in multi-layered dielectric layer can improve the step coverage in the following manufacturing process.
摘要翻译：一种多层电介质层的制造方法和结构，用于在方向层上形成用于提高集成电路的一体化的开口的步骤，步骤覆盖的能力以及由悬垂结构引起的问题，其中多个开口的倾斜侧壁层状电介质层可以在以下制造过程中改善步骤覆盖。

8. 发明授权

US06235608B1 STI process by method of in-situ multilayer dielectric deposition 有权
标题翻译： STI工艺采用原位多层电介质沉积法
公开(公告)号：US06235608B1
公开(公告)日：2001-05-22
申请号：US09292772
申请日：1999-04-14
申请人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
发明人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
IPC分类号： H01L21336
CPC分类号： H01L21/31144 , H01L21/31053 , H01L21/31612 , H01L21/3185 , H01L21/76224 , Y10S438/97
摘要： A process for forming shallow trench isolation (STI) structures. It includes the steps of: (a) depositing a composite silicon nitride on to the silicon substrate; (b) forming a shallow trench on the silicon substrate by etching, using the composite silicon nitride as the hard mask; (c) depositing a filler oxide layer inside the shallow trench as well as on top of the composite silicon nitride, using a chemical vapor deposition (CVD) method; and (d) using a chemical-mechanical polishing (CMP) process to planarize the filler oxide layer using the composite nitride as a CMP stop. The composite silicon nitride comprises a plurality of silicon nitride layers whose CMP removal rate increases with the distance from the silicon substrate. Additionally, a composite silicon oxide layer can be formed on top of the filler oxide layer which comprises a plurality of silicon oxide layers whose CMP removal rate increases with the distance from the silicon substrate.
摘要翻译：一种用于形成浅沟槽隔离（STI）结构的工艺。它包括以下步骤：（a）将复合氮化硅沉积到硅衬底上; （b）使用复合氮化硅作为硬掩模，通过蚀刻在硅衬底上形成浅沟槽; （c）使用化学气相沉积（CVD）方法在浅沟槽内以及在复合氮化硅的顶部上沉积填充氧化物层; 和（d）使用化学机械抛光（CMP）工艺来使用复合氮化物作为CMP停止层来平坦化填充氧化物层。复合氮化硅包括多个氮化硅层，其CMP去除率随着与硅衬底的距离而增加。此外，可以在填充氧化物层的顶部上形成复合氧化硅层，其包括多个氧化硅层，其CMP去除速率随着与硅衬底的距离而增加。

9. 发明授权

US5969409A Combined in-situ high density plasma enhanced chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP) process to form an intermetal dielectric layer with a stopper layer embedded therein 有权
公开(公告)号：US5969409A
公开(公告)日：1999-10-19
申请号：US249509
申请日：1999-02-12
申请人： Chi-Fa Lin
发明人： Chi-Fa Lin
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/532 , H01L21/28
CPC分类号： H01L23/5329 , H01L21/31053 , H01L21/31055 , H01L21/76819 , H01L2924/0002
摘要： A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a highest etching/depositing component ratio and thus the lowest CMP removal rate; (c) forming a third HDP-CVD layer on the second HDP-CVD layer using the same HDP-CVD process but with a third HDP-CVD composition having a low etching/depositing component ratio and thus a high CMP removal rate; and (d) using a chemical mechanical process to remove at least a part of the third HDP-CVD layer using the second HDP-CVD layer as a stopper. All the three HDP-CVD compositions contain the same etching and silicon-containing deposition components so as to improve the CMP efficiency without incurring substantially increased fabrication cost.

10. 发明授权

US5920792A High density plasma enhanced chemical vapor deposition process in combination with chemical mechanical polishing process for preparation and planarization of intemetal dielectric layers 失效
标题翻译：高密度等离子体增强化学气相沉积工艺结合化学机械抛光工艺制备和平坦化介质层
公开(公告)号：US5920792A
公开(公告)日：1999-07-06
申请号：US45101
申请日：1998-03-19
申请人： Chi-Fa Lin
发明人： Chi-Fa Lin
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/00
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/31053 , H01L21/31612
摘要： A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a lower etching/depositing component ratio and thus a higher CMP removal rate; and (c) using a chemical mechanical process to remove at least a part of the second HDP-CVD layer using the first HDP-CVD layer as a stopper. A protective layer with the same etching/deposition components but a different ratio than the sacrificial layer can be deposited on the sacrificial layer to minimize the dishing effect during the initial stage of the chemical mechanical polishing process.
摘要翻译：公开了利用组合的高密度等离子体化学气相沉积（HDP-CVD）工艺和化学机械抛光（CMP）工艺的晶片平面化工艺。该方法包括以下步骤：（a）使用具有较高蚀刻/沉积成分比率的第一HDP-CVD组合物，从而降低CMP去除率，在半导体晶片的表面上形成第一HDP-CVD层; （b）使用相同的HDP-CVD工艺在第一HDP-CVD层上形成第二HDP-CVD层，但是使用具有较低蚀刻/沉积成分比的第二HDP-CVD组合物，因此具有较高的CMP去除率; 和（c）使用化学机械方法，使用第一HDP-CVD层作为塞子去除第二HDP-CVD层的至少一部分。具有相同蚀刻/沉积组分但与牺牲层不同的比例的保护层可以沉积在牺牲层上，以使化学机械抛光过程的初始阶段期间的凹陷效应最小化。

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