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    • 1. 发明申请
    • Power Amplifier for Amplifying High-Frequency (H.F.) Signals
    • 用于放大高频(H.F)信号的功率放大器
    • US20080265997A1
    • 2008-10-30
    • US11719893
    • 2005-11-10
    • Manfred BerrothLei Wu
    • Manfred BerrothLei Wu
    • H03F3/21
    • H03F3/195H03F1/0277H03F1/223H03F1/52H03F1/523H03F3/211H03F3/423H03F3/604H03F3/72H03F2200/451H03F2203/7215
    • An H.F. power amplifier is disclosed having a plurality of branches (10, 11, 12) switched in parallel. Each branch comprises a plurality of amplifier elements (T1, T4) switched in series. Resistors (R2, R5) enable the voltage (U_DS) applied to the amplifier elements (T1, T4) to be set at a fraction of a supply voltage (Ud) applied to the branches (10, 11, 12). Capacitors (C2, C4) are used to adjust the source impedance of the amplifier elements (T2, T4). In order to prevent the gate-drain voltage (U_GD) from exceeding the breakdown voltage of an amplifier element (T1, T4) and damaging the amplifier element (T1, T4), a limiting path (7) is connected according to the invention between the gate terminal (G) and the drain terminal (D) of the amplifier element (T1, T4), the limiting path (7) being switchable between a conducting state and a blocking state depending on the gate-drain voltage (U_GD).
    • 公开了具有并行切换的多个分支(10,11,12)的功率放大器。 每个分支包括串联交换的多个放大器元件(T 1,T 4)。 电阻器(R 2,R 5)使得施加到放大器元件(T 1,T 4)的电压(U_DS)被设置为施加到分支(10,11,12)的电源电压(Ud)的分数, 。 电容器(C 2,C 4)用于调节放大器元件(T 2,T 4)的源阻抗。 为了防止栅极 - 漏极电压(U_GD)超过放大器元件(T 1,T 4)的击穿电压并损坏放大器元件(T 1,T 4),限制路径(7)根据 对于放大器元件(T 1,T 4)的栅极端子(G)和漏极端子(D)之间的发明,限制路径(7)可根据栅极 - 漏极电压(U_GD)。
    • 2. 发明授权
    • Power amplifier for amplifying high-frequency (H.F.) signals
    • 用于放大高频(H.F.)信号的功率放大器
    • US07551036B2
    • 2009-06-23
    • US11719893
    • 2005-11-10
    • Manfred BerrothLei Wu
    • Manfred BerrothLei Wu
    • H03F3/04
    • H03F3/195H03F1/0277H03F1/223H03F1/52H03F1/523H03F3/211H03F3/423H03F3/604H03F3/72H03F2200/451H03F2203/7215
    • An H.F. power amplifier is disclosed having a plurality of branches (10, 11, 12) switched in parallel. Each branch comprises a plurality of amplifier elements (T1, T4) switched in series. Resistors (R2, R5) enable the voltage (U_DS) applied to the amplifier elements (T1, T4) to be set at a fraction of a supply voltage (Ud) applied to the branches (10, 11, 12). Capacitors (C2, C4) are used to adjust the source impedance of the amplifier elements (T2, T4). In order to prevent the gate-drain voltage (U_GD) from exceeding the breakdown voltage of an amplifier element (T1, T4) and damaging the amplifier element (T1, T4), a limiting path (7) is connected according to the invention between the gate terminal (G) and the drain terminal (D) of the amplifier element (T1, T4), the limiting path (7) being switchable between a conducting state and a blocking state depending on the gate-drain voltage (U_GD).
    • 公开了具有并行切换的多个分支(10,11,12)的功率放大器。 每个分支包括串联切换的多个放大器元件(T1,T4)。 电阻器(R2,R5)使得施加到放大器元件(T1,T4)的电压(U_DS)被设置为施加到分支(10,11,12)的电源电压(Ud)的一小部分。 电容器(C2,C4)用于调节放大器元件(T2,T4)的源阻抗。 为了防止栅极 - 漏极电压(U_GD)超过放大器元件(T1,T4)的击穿电压并损坏放大器元件(T1,T4),根据本发明,限制路径(7)连接在 放电元件(T1,T4)的栅极端子(G)和漏极端子(D),限制路径(7)可根据栅极 - 漏极电压(U_GD)在导通状态和阻塞状态之间切换。
    • 4. 发明授权
    • Visual language modeling for image classification
    • 图像分类的视觉语言建模
    • US08126274B2
    • 2012-02-28
    • US11847959
    • 2007-08-30
    • Mingjing LiWei-Ying MaZhiwei LiLei Wu
    • Mingjing LiWei-Ying MaZhiwei LiLei Wu
    • G06K9/62
    • G06K9/4685G06K9/4642G06K9/6278
    • Systems and methods for visual language modeling for image classification are described. In one aspect the systems and methods model training images corresponding to multiple image categories as matrices of visual words. Visual language models are generated from the matrices. In view of a given image, for example, provided by a user or from the Web, the systems and methods determine an image category corresponding to the given image. This image categorization is accomplished by maximizing the posterior probability of visual words associated with the given image over the visual language models. The image category, or a result corresponding to the image category, is presented to the user.
    • 描述了用于图像分类的视觉语言建模的系统和方法。 在一个方面,系统和方法将对应于多个图像类别的训练图像建模为视觉词的矩阵。 视觉语言模型是从矩阵生成的。 考虑到例如由用户或从Web提供的给定图像,系统和方法确定对应于给定图像的图像类别。 这种图像分类是通过在视觉语言模型上最大化与给定图像相关联的视觉词的后验概率来实现的。 图像类别或与图像类别对应的结果被呈现给用户。
    • 5. 发明授权
    • Architectures, circuits, systems and methods for reducing latency in data communications
    • 用于减少数据通信延迟的架构,电路,系统和方法
    • US07835425B1
    • 2010-11-16
    • US12330218
    • 2008-12-08
    • Pantas SutardjaLei WuHongying Sheng
    • Pantas SutardjaLei WuHongying Sheng
    • H03K11/00H04L25/60H04L25/64
    • G06F13/405
    • Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.
    • 用于促进数据通信和/或减少数据通信中的延迟的电路,架构,系统和方法。 该架构包括时钟恢复环路,其接收来自主机设备的数据并提供恢复的时钟信号,滤波器电路接收恢复的时钟信号信息,并提供响应于恢复的时钟信号信息和两个时钟信号调整发射机时钟的控制信号 以及接收控制信号并根据发射机时钟向目的地设备发送数据的发射机。 电路通常包括时钟对准块,其接收第一和第二周期信号并响应于此提供控制信号,用于第一周期性信号信息的滤波器以及被配置为组合控制信号和滤波信息的逻辑电路,由此提供调整 信号用于第二周期信号。 系统通常涉及包括本架构和/或电路的系统。 该方法通常包括确定第一和第二周期信号之间的相位差,从数据流中恢复一个周期信号; 响应于来自恢复的周期信号的相位差和滤波信息调整另一周期信号; 以及根据所述调整的周期信号发送数据流。 本发明有利地消除数据路径中的FIFO存储器,从而减少收发机等待时间并提高系统性能。