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1. 发明授权

US5698869A Insulated-gate transistor having narrow-bandgap-source 失效
标题翻译：具有窄带隙源的绝缘栅晶体管
公开(公告)号：US5698869A
公开(公告)日：1997-12-16
申请号：US527515
申请日：1995-09-13
申请人： Makoto Yoshimi , Satoshi Inaba , Atsushi Murakoshi , Mamoru Terauchi , Naoyuki Shigyo , Yoshiaki Matsushita , Masami Aoki , Takeshi Hamamoto , Yutaka Ishibashi , Tohru Ozaki , Hitomi Kawaguchiya , Kazuya Matsuzawa , Osamu Arisumi , Akira Nishiyama
发明人： Makoto Yoshimi , Satoshi Inaba , Atsushi Murakoshi , Mamoru Terauchi , Naoyuki Shigyo , Yoshiaki Matsushita , Masami Aoki , Takeshi Hamamoto , Yutaka Ishibashi , Tohru Ozaki , Hitomi Kawaguchiya , Kazuya Matsuzawa , Osamu Arisumi , Akira Nishiyama
IPC分类号： H01L21/336 , H01L27/12 , H01L29/786 , H01L31/072
CPC分类号： H01L29/66666 , H01L27/1203 , H01L29/66772 , H01L29/78618 , H01L29/78681
摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.
摘要翻译：提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生。此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

2. 发明授权

US5629539A Semiconductor memory device having cylindrical capacitors 失效
标题翻译：具有圆柱形电容器的半导体存储器件
公开(公告)号：US5629539A
公开(公告)日：1997-05-13
申请号：US400887
申请日：1995-03-08
申请人： Masami Aoki , Tohru Ozaki , Takashi Yamada , Hitomi Kawaguchiya
发明人： Masami Aoki , Tohru Ozaki , Takashi Yamada , Hitomi Kawaguchiya
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/10817 , H01L29/94
摘要： A semiconductor memory device comprises a semiconductor substrate, a plurality of memory cells including a plurality of MOS transistors, each having a source, a drain and a gate, and a plurality of capacitors formed on the semiconductor substrate in a matrix manner, an interlayer insulating film formed on the memory cells and having a plurality of openings selectively formed, a plurality of plug electrodes formed in the openings of the interlayer insulating film, a plurality of bit lines, each bit line being connected to one of the source and the drain of each of the MOS transistors through a corresponding one of the plug electrodes, and a plurality word lines, each word line being the gate of each of the MOS transistors. The capacitors each comprise a storage node electrode having a cylindrical portion layered on another one of the source and the drain of each of the MOS transistors, a capacitor dielectric film formed on the storage node electrode, and a plate electrode formed to be opposed to at least the storage node electrode interposing the capacitor dielectric film therebetween. The bit lines are formed on the interlayer insulating film and connected to the upper surface of the plug electrode. The plug electrode has a pad electrode comprised of a lower side conductive member formed with a same layer as the storage node electrode and a cylindrical side wall conductive member, and an upper side conductive member formed on the pad electrode.
摘要翻译：半导体存储器件包括半导体衬底，包括多个MOS晶体管的多个存储单元，每个MOS晶体管具有源极，漏极和栅极以及以矩阵方式形成在半导体衬底上的多个电容器，层间绝缘形成在存储单元上并具有选择性地形成的多个开口的多个插塞电极，形成在层间绝缘膜的开口中的多个插塞电极，多个位线，每个位线连接到源极和漏极之一每个MOS晶体管通过相应的一个插头电极和多个字线，每个字线是每个MOS晶体管的栅极。电容器各自包括存储节点电极，其具有层叠在每个MOS晶体管的源极和漏极的另一个上的圆柱形部分，形成在存储节点电极上的电容器电介质膜和形成为与存储节点电极至少插入电容器电介质膜之间。位线形成在层间绝缘膜上并连接到插塞电极的上表面。插头电极具有由形成有与蓄电节点电极相同层的下侧导电部件和圆筒状侧壁导电部件构成的焊盘电极，以及形成在焊盘电极上的上侧导电部件。

3. 发明授权

US5838038A Dynamic random access memory device with the combined open/folded bit-line pair arrangement 失效
标题翻译：具有组合打开/折叠位线对布置的动态随机存取存储器件
公开(公告)号：US5838038A
公开(公告)日：1998-11-17
申请号：US478620
申请日：1995-06-07
申请人： Daisaburo Takashima , Shigeyoshi Watanabe , Tohru Ozaki , Takeshi Hamamoto , Yukihito Oowaki
发明人： Daisaburo Takashima , Shigeyoshi Watanabe , Tohru Ozaki , Takeshi Hamamoto , Yukihito Oowaki
IPC分类号： G11C7/18 , H01L27/108
CPC分类号： G11C7/18 , G11C2211/4013
摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.
摘要翻译：半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极另一个源极和漏极到存储电极。

4. 发明授权

US5747844A Dynamic semiconductor memory device with higher density bit line/word line layout 失效
公开(公告)号：US5747844A
公开(公告)日：1998-05-05
申请号：US736279
申请日：1996-10-24
申请人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
发明人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
IPC分类号： H01L21/822 , G11C11/401 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/0207 , H01L27/10852 , H01L27/10882 , Y10S257/907
摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

5. 发明授权

US6153476A Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US6153476A
公开(公告)日：2000-11-28
申请号：US30127
申请日：1998-02-25
申请人： Satoshi Inaba , Tohru Ozaki , Yusuke Kohyama , Kazumasa Sunouchi
发明人： Satoshi Inaba , Tohru Ozaki , Yusuke Kohyama , Kazumasa Sunouchi
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/04 , H01L27/088 , H01L27/105 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/108 , Y10S257/90
摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

6. 发明授权

US06635933B2 Structure of a capacitor section of a dynamic random-access memory 失效
公开(公告)号：US06635933B2
公开(公告)日：2003-10-21
申请号：US09953306
申请日：2001-09-17
申请人： Yutaka Ishibashi , Yusuke Kohyama , Tohru Ozaki
发明人： Yutaka Ishibashi , Yusuke Kohyama , Tohru Ozaki
IPC分类号： H01L2976
CPC分类号： H01L27/10885 , H01L27/10852 , H01L27/10873 , H01L28/91
摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

7. 发明授权

US06303429B1 Structure of a capacitor section of a dynamic random-access memory 失效
标题翻译：动态随机存取存储器的电容器部分的结构
公开(公告)号：US06303429B1
公开(公告)日：2001-10-16
申请号：US09676084
申请日：2000-10-02
申请人： Yutaka Ishibashi , Yusuke Kohyama , Tohru Ozaki
发明人： Yutaka Ishibashi , Yusuke Kohyama , Tohru Ozaki
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L27/10852 , H01L27/10873 , H01L28/91
摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.
摘要翻译：电容器形成在由氧化硅制成的层间绝缘体中制成的沟槽中。绝缘膜（例如，氮化硅膜）设置在层间绝缘体的每个沟槽的侧面上。在层间绝缘体的每个沟槽中设置由钌等制成的存储电极。在存储电极上形成由BSTO等构成的电容绝缘膜。在电容器绝缘膜上形成由钌等制成的平板电极。平板电极对所有提供的电容器是共同的。任何两个相邻的电容器通过层间绝缘体和设置在层间绝缘体的沟槽的侧面上的绝缘膜电隔离。

8. 发明授权

US06448618B1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06448618B1
公开(公告)日：2002-09-10
申请号：US09640707
申请日：2000-08-18
申请人： Satoshi Inaba , Tohru Ozaki , Yusuke Kohyama , Kazumesa Sunouchi
发明人： Satoshi Inaba , Tohru Ozaki , Yusuke Kohyama , Kazumesa Sunouchi
IPC分类号： H01L27108
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/108 , Y10S257/90
摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.
摘要翻译：在DRAM中，基于最小设计规则，在半导体衬底上的单元区域中形成多个第一MOSFET，并且在侧壁部分上形成具有侧壁绝缘膜的第一栅极侧壁每个第一MOSFET的第一栅电极。在半导体衬底上的外围电路区域中形成至少一个第二MOSFET，并且在第二MOSFET的第二栅电极的侧壁部分上形成具有侧壁绝缘膜的第二栅极侧壁。能够形成与第一栅电极自对准的精细接触孔的第一MOSFET和能够在抑制短沟道效应的同时充分减轻寄生电阻的第二MOSFET同时形成基质。

9. 发明授权

US6078073A Semiconductor apparatus formed by SAC (self-aligned contact) method and manufacturing method therefor 失效
标题翻译：由SAC（自对准接触）方法形成的半导体装置及其制造方法
公开(公告)号：US6078073A
公开(公告)日：2000-06-20
申请号：US878208
申请日：1997-06-18
申请人： Mariko Habu , Kazumasa Sunouchi , Masami Aoki , Tohru Ozaki
发明人： Mariko Habu , Kazumasa Sunouchi , Masami Aoki , Tohru Ozaki
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10844 , H01L21/76897 , H01L27/10873
摘要： A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.
摘要翻译：在形成在半导体衬底上的栅绝缘膜上形成具有层叠在其上部的第一绝缘膜的栅电极。在栅电极的侧壁上形成侧壁，并且形成绝缘膜以覆盖栅电极和侧壁。通过绝缘膜进行离子注入，从而在半导体衬底上形成扩散层。形成层间电介质膜，然后选择性地蚀刻层间电介质膜和绝缘膜，从而以与栅电极自对准的方式形成露出栅极绝缘膜的开口部。然后，去除开口部的底部的栅极绝缘膜，使得露出半导体基板的表面。然后，形成与半导体基板的露出面连接的布线层。

10. 发明授权

US5578847A Dynamic semiconductor memory device with higher density bit line/word line layout 失效
标题翻译：具有更高密度位线/字线布局的动态半导体存储器件
公开(公告)号：US5578847A
公开(公告)日：1996-11-26
申请号：US402570
申请日：1995-03-13
申请人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
发明人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
IPC分类号： H01L21/822 , G11C11/401 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/0207 , H01L27/10852 , H01L27/10882 , Y10S257/907
摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.
摘要翻译：设置在一个位线BL上的多个位线触点布置在每个设置在每个相邻的两个字线WL之间的每隔一个空间中，并且设置在相邻位线BL上的多个位线触点彼此布置每个相邻的两个字线WL之间的空间不同于其中布置在前位线上形成的位线触点中的相应一个的空间。

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