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1. 发明授权

US6126915A Titanium dioxide reduced in volatile water content, process for producing the same, and masterbatch containing the same 有权
标题翻译：二氧化钛的挥发性水分含量降低，生产过程中产生的二氧化钛和含有相同的母料
公开(公告)号：US6126915A
公开(公告)日：2000-10-03
申请号：US91884
申请日：1998-08-26
申请人： Makoto Tunashima , Kazuyoshi Muraoka , Kohji Yamamoto , Susumu Miyasita , Noburu Sakuma , Masaru Hosokawa
发明人： Makoto Tunashima , Kazuyoshi Muraoka , Kohji Yamamoto , Susumu Miyasita , Noburu Sakuma , Masaru Hosokawa
IPC分类号： C01G23/047 , C01G23/053 , C08J3/22 , C08K3/22 , C09C1/36 , C01G25/02 , C08K9/10
CPC分类号： C01G23/047 , C01G23/0532 , C08J3/22 , C08K3/22 , C09C1/3661 , C09C1/3684 , C01P2004/62 , C01P2006/22 , C01P2006/60 , C01P2006/80 , C01P2006/82 , C08K2003/2237
摘要： Titanium dioxide powder with a greatly decreased volatile moisture content can be obtained by surface treating with titanium dioxide powder with addition of a calcium salt and/or a silane coupling agent, or by a surface treatment by addition of an aluminate together with these surface treatments. A masterbatch containing this titanium dioxide powder is of high quality, having no defect due to foam generation upon high temperature processing.
摘要翻译： PCT No.PCT / JP96 / 03844 Sec。 371日期：1998年8月26日 102（e）1998年8月26日PCT 1996年12月27日PCT PCT。出版物WO97 / 24289 PCT 日期1997年7月10日可以通过用二氧化钛粉末加入钙盐和/或硅烷偶联剂进行表面处理，或通过加入铝酸盐进行表面处理，可以获得挥发性水分含量大大降低的二氧化钛粉末用这些表面处理。含有这种二氧化钛粉末的母料是高质量的，由于在高温处理时产生泡沫而没有缺陷。

2. 发明授权

US6113873A Stable anatase titanium dioxide and process for preparing the same 失效
标题翻译：稳定的锐钛型二氧化钛及其制备方法
公开(公告)号：US6113873A
公开(公告)日：2000-09-05
申请号：US91742
申请日：1998-07-29
申请人： Makoto Tunashima , Kazuyoshi Muraoka , Kohji Yamamoto , Masaru Mikami , Suzuo Sasaki
发明人： Makoto Tunashima , Kazuyoshi Muraoka , Kohji Yamamoto , Masaru Mikami , Suzuo Sasaki
IPC分类号： C01G23/047 , C01G23/053 , C09C1/36
CPC分类号： C09C1/3692 , C01G23/047 , C01G23/0532 , C09C1/3653 , C01P2002/50 , C01P2004/62 , C01P2006/60 , C01P2006/80
摘要： To hydrous titanium dioxide obtained by hydrolysis of titanium sulfate was added a predetermined amount of a water-soluble aluminum compound and/or a water-soluble zinc compound, the mixture is calcined, and a suitable amount of aluminum and/or zinc is introduced into the crystals to make up the crystal defects of anatase-type titanium dioxide, so that it has increased stability and excellent color stability.
摘要翻译： PCT No.PCT / JP96 / 03843 Sec。 371日期：1998年6月24日 102（e）1998年6月24日PCT 1996年12月27日PCT公布。公开号WO97 / 24288 PCT 日期1997年7月10日对通过硫酸钛水解得到的含水二氧化钛加入预定量的水溶性铝化合物和/或水溶性锌化合物，将该混合物煅烧，并加入适量的铝和/ 或者将锌引入晶体中以弥补锐钛矿型二氧化钛的晶体缺陷，使其具有增加的稳定性和优异的颜色稳定性。

3. 发明授权

US5831421A Semiconductor device with supply voltage-lowering circuit 失效
标题翻译：具有电源降压电路的半导体器件
公开(公告)号：US5831421A
公开(公告)日：1998-11-03
申请号：US837461
申请日：1997-04-18
申请人： Takashi Taira , Kazuyoshi Muraoka
发明人： Takashi Taira , Kazuyoshi Muraoka
IPC分类号： H01L27/04 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , H01L21/822 , G05F3/16
CPC分类号： G05F1/465
摘要： A semiconductor device includes an internal circuit and first and second supply voltage-lowering circuits in its semiconductor chip. The first supply voltage-lowering circuit steps down an external power supply potential of the semiconductor chip in response to a control signal, generates a first internal power supply potential, and supplies it to the internal circuit. The second supply voltage-lowering circuit steps down the external power supply potential of the semiconductor chip in response to the control signal, generates a second internal power supply potential of substantially the same level as that of the first internal power supply potential, and supplies it to the internal circuit. The first and second internal power supply potentials output from the first and second supply voltage-lowering circuits vary out of phase with each other to cancel out variations in first and second internal power supply potentials.
摘要翻译：半导体器件包括其半导体芯片中的内部电路和第一和第二电源降压电路。第一电源降压电路响应于控制信号降低半导体芯片的外部电源电位，产生第一内部电源电位，并将其提供给内部电路。第二电源降压电路响应于控制信号降低半导体芯片的外部电源电位，产生与第一内部电源电位基本相同的第二内部电源电位，并将其提供到内部电路。从第一和第二电源电压降低电路输出的第一和第二内部电源电位彼此不同相异，以抵消第一和第二内部电源电位的变化。

4. 发明授权

US5402010A Semiconductor device including internal circuit having both states of active/precharge 失效
标题翻译：半导体器件包括具有两种状态的有源/预充电的内部电路
公开(公告)号：US5402010A
公开(公告)日：1995-03-28
申请号：US56408
申请日：1993-05-04
申请人： Kazuyoshi Muraoka
发明人： Kazuyoshi Muraoka
IPC分类号： G11C11/401 , G11C7/20 , G11C7/22 , G11C11/409 , G11C11/34
CPC分类号： G11C7/20 , G11C7/22
摘要： A semiconductor device has a plurality of internal circuits capable of having two conditions of an active state and a precharge state in the internal circuits. The device comprises signal generation element for generating a first signal which causes said internal circuits to be initialized until satisfying a predetermined condition from a time when the power is supplied; and state set element which is connected to an external apparatus through an interface which is supplied an external state signal, and for setting a precharge state of the internal circuits by outputting an internal state signal corresponding to the external state signal in response to a supply of the first signal from the signal generation element.
摘要翻译：半导体器件具有能够在内部电路中具有两种状态的激活状态和预充电状态的多个内部电路。该装置包括用于产生第一信号的信号产生元件，该第一信号使得所述内部电路被初始化，直到从供电时起满足预定条件; 以及状态设定元件，其通过提供外部状态信号的接口连接到外部设备，并且用于通过输出与外部状态信号相对应的内部状态信号来设置内部电路的预充电状态，来自信号发生元件的第一信号。

5. 发明授权

US5270971A Semiconductor memory having a plurality of sense amplifier circuits and corresponding bit lines 失效
标题翻译：半导体存储器具有多个读出放大器电路和对应的位线
公开(公告)号：US5270971A
公开(公告)日：1993-12-14
申请号：US677442
申请日：1991-03-29
申请人： Kazuyoshi Muraoka , Masaru Koyanagi , Minoru Yamada
发明人： Kazuyoshi Muraoka , Masaru Koyanagi , Minoru Yamada
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C7/00
CPC分类号： G11C7/065
摘要： An improved semiconductor memory having a plurality of sense amplifier circuits corresponding to each bit line of a plurality of columns. A first common line is connected in common to the sense amplifier circuits, and a second common line is connected to the first common line. A first switching element is connected between the second common line and a reference voltage potential terminal, and a second switching element is connected to the first common line and the reference voltage potential. The second switching element corresponding to the first common line connected to one of the sense amplifier circuits is made conductive in response to a selection of the sense amplifier is disclosed.

6. 发明申请

US20060146620A1 Semiconductor memory having a spare memory cell 失效
公开(公告)号：US20060146620A1
公开(公告)日：2006-07-06
申请号：US11363933
申请日：2006-03-01
申请人： Makoto Hamada , Kazuyoshi Muraoka , Masahiro Yoshihara
发明人： Makoto Hamada , Kazuyoshi Muraoka , Masahiro Yoshihara
IPC分类号： G11C29/00 , G11C17/18
CPC分类号： G11C29/027 , G11C29/02
摘要： A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.

7. 发明授权

US06680873B2 Semiconductor device having electric fuse element 失效
标题翻译：具有电熔丝元件的半导体器件
公开(公告)号：US06680873B2
公开(公告)日：2004-01-20
申请号：US10042937
申请日：2002-01-08
申请人： Kazuyoshi Muraoka , Eiji Kozuka
发明人： Kazuyoshi Muraoka , Eiji Kozuka
IPC分类号： G11C800
CPC分类号： G11C29/785 , G11C17/16 , G11C17/18
摘要： The output terminal of a voltage generation circuit is connected to one end portion of a fuse circuit. A transistor is connected to the other end portion of the fuse circuit. In program mode, a voltage generated from the voltage generation circuit is applied to the fuse circuit and a current flows through the fuse circuit and the transistor. In verify mode, a current generated from the voltage generation circuit flows into a pad through a selected fuse circuit and a detection circuit.
摘要翻译：电压产生电路的输出端连接到熔丝电路的一端。晶体管连接到熔丝电路的另一端部。在编程模式中，从电压产生电路产生的电压被施加到熔丝电路，并且电流流过熔丝电路和晶体管。在验证模式下，从电压产生电路产生的电流通过选定的熔丝电路和检测电路流入焊盘。

8. 发明授权

US5813210A Twisting method and twisting frame utilizing I/F fluctuations 失效
标题翻译：采用I / F波动的扭转方式和扭转框架
公开(公告)号：US5813210A
公开(公告)日：1998-09-29
申请号：US853417
申请日：1997-05-09
申请人： Toshimitsu Musha , Yuichi Yanai , Kazuyoshi Muraoka , Yuki Niwa , Yasuo Nakano
发明人： Toshimitsu Musha , Yuichi Yanai , Kazuyoshi Muraoka , Yuki Niwa , Yasuo Nakano
IPC分类号： D01H1/00 , D02G3/34 , D01H7/46
CPC分类号： D02G3/34 , D01H1/006
摘要： A twisting frame 1, and a method of twisting yarn 11 in which a twist is applied to the yarn by signals having a 1/f fluctuation to yield a yarn 11 in which the yarn count varies with a 1/f fluctuation. The first aspect is a twisting method that applies twist to a single yarn or a plural number of yarns, in which a twist is applied to the yarn or yarns by setting the twist count to correspond to the strengths of serial signals having a 1/f fluctuation.
摘要翻译：扭转框架1以及通过具有1 / f波动的信号对纱线施加扭曲的纱线11的捻合方法，从而产生纱线数1变化的纱线11。第一方面是一种扭转方法，其对单纱或多根纱线施加扭曲，其中通过将捻数计算为对应于具有1 / f的串行信号的强度而对纱线或纱线施加扭曲波动。

9. 发明授权

US5768204A Semiconductor memory device having dummy word lines and method for controlling the same 失效
标题翻译：具有虚拟字线的半导体存储器件及其控制方法
公开(公告)号：US5768204A
公开(公告)日：1998-06-16
申请号：US661948
申请日：1996-06-11
申请人： Kazuyoshi Muraoka
发明人： Kazuyoshi Muraoka
IPC分类号： G11C11/401 , G11C7/06 , G11C7/14 , G11C11/408 , G11C11/409 , G11C7/00
CPC分类号： G11C7/14 , G11C11/4087 , G11C7/065
摘要： Memory cells and a sense amplifier are connected to a pair of bit lines. Two dummy word lines are capacitively coupled with the pair of bit lines. One of the dummy word lines is driven to a high level before the sense amplifier starts the sense operation, and the other dummy word line is driven to a high level after the sense amplifier has started the sense operation. When the sense amplifier has terminated the sense operation, the two dummy word lines are driven to a low level.
摘要翻译：存储单元和读出放大器连接到一对位线。两个虚拟字线与该对位线电容耦合。在读出放大器开始感测操作之前，虚拟字线之一被驱动到高电平，并且在读出放大器已经开始感测操作之后将另一个虚拟字线驱动到高电平。当读出放大器终止感测操作时，两个虚拟字线被驱动到低电平。

10. 发明授权

US5752295A 1 F blended yarn spinning method and blended yarn spinning frame 失效
标题翻译： 1 / f混纺纱线纺丝法和混纺纱线纺纱机
公开(公告)号：US5752295A
公开(公告)日：1998-05-19
申请号：US674718
申请日：1996-07-02
申请人： Toshimitsu Musha , Yuichi Yanai , Kazuyoshi Muraoka , Yuki Niwa
发明人： Toshimitsu Musha , Yuichi Yanai , Kazuyoshi Muraoka , Yuki Niwa
IPC分类号： D02G3/04 , D01H5/36 , D01H7/02 , D02G3/34 , D01H5/00 , D01H7/00
CPC分类号： D02G3/34 , D01H5/36
摘要： In the blending and spinning processes, 1/f fluctuation signals are imparted to the feed slivers or rovings, wherein the blending ratio of the blended slivers, blended rovings, or blended yarn varies with a correlation, specifically a correlation with a 1/f fluctuation.
摘要翻译：在混纺和纺丝过程中，1 / f波动信号被赋予进料条或粗纱，其中混合纱条，混纺粗纱或混纺纱线的混合比随相关性变化，特别是与1 / f波动的相关性。

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