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1. 发明授权

US08576608B2 Memory apparatus 有权
标题翻译：存储设备
公开(公告)号：US08576608B2
公开(公告)日：2013-11-05
申请号：US13310839
申请日：2011-12-05
申请人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
发明人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0042 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146
摘要： A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.
摘要翻译：存储装置包括：多个存储单元，包括第一电阻变化元件; 以及读出电路，其通过将从所述多个存储单元中选择的存储单元的电阻状态与参考存储单元的电阻状态进行比较来确定所述第一电阻变化元件的电阻值的大小，其中所述参考存储器单元包括第二电阻变化元件，第二电阻变化元件相对于施加电压的电阻值小于第一电阻变化元件的高电阻状态的电阻值，第二电阻变化元件显示相同的电阻变化特征为第一电阻变化元件。

2. 发明申请

US20120212994A1 MEMORY APPARATUS 有权
标题翻译：记忆装置
公开(公告)号：US20120212994A1
公开(公告)日：2012-08-23
申请号：US13310839
申请日：2011-12-05
申请人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
发明人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0042 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146
摘要： A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.
摘要翻译：存储装置包括：多个存储单元，包括第一电阻变化元件; 以及读出电路，其通过将从所述多个存储单元中选择的存储单元的电阻状态与参考存储单元的电阻状态进行比较来确定所述第一电阻变化元件的电阻值的大小，其中所述参考存储器单元包括第二电阻变化元件，第二电阻变化元件相对于施加电压的电阻值小于第一电阻变化元件的高电阻状态的电阻值，第二电阻变化元件显示相同的电阻变化特征为第一电阻变化元件。

3. 发明申请

US20120026777A1 Variable-resistance memory device 失效
标题翻译：可变电阻存储器件
公开(公告)号：US20120026777A1
公开(公告)日：2012-02-02
申请号：US13067933
申请日：2011-07-08
申请人： Makoto Kitagawa , Hiroshi Yoshihara
发明人： Makoto Kitagawa , Hiroshi Yoshihara
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C7/12 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0073 , G11C2213/56 , G11C2213/79
摘要： Disclosed herein is a variable-resistance memory device including: a memory-cell array employing a plurality of memory cells each including a storage element having a resistance varying in accordance with the direction of a voltage applied to the storage element and including an access transistor connected in series to the storage element between a bit line and a source line; and a voltage supplying circuit for setting a read voltage used for reading out the resistance of the storage element on a selected bit line connected to the memory cell serving as a read object in an operation to supply the read voltage to the selected bit line.
摘要翻译：这里公开了一种可变电阻存储器件，包括：存储单元阵列，其采用多个存储单元，每个存储单元包括存储元件，存储元件具有根据施加到存储元件的电压的方向而变化的电阻，并且包括存取晶体管，与位线和源极线之间的存储元件串联; 以及电压提供电路，用于在将读取电压提供给所选择的位线的操作中设置用于读出连接到用作读取对象的存储单元的选定位线上的存储元件的电阻的读取电压。

4. 发明授权

US08379430B2 Memory device and method of reading memory device 失效
标题翻译：存储器件和读取存储器件的方法
公开(公告)号：US08379430B2
公开(公告)日：2013-02-19
申请号：US12923978
申请日：2010-10-19
申请人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
发明人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0061 , G11C2013/0054 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.
摘要翻译：存储装置包括：存储单元，其中两个电极之间的电荷放电速率根据所存储信息的逻辑而不同; 读出放大器，通过将存储单元的一个电极与其连接的布线的放电电位与参考电位进行比较来检测信息的逻辑; 以及复制电路，其具有仿真存储器单元的复制单元，并且根据复制单元的放电速率来控制读出放大器的感测时序。

5. 发明申请

US20110305068A1 RESISTANCE RANDOM ACCESS CHANGE MEMORY DEVICE 审中-公开
标题翻译：电阻随机访问更改存储器件
公开(公告)号：US20110305068A1
公开(公告)日：2011-12-15
申请号：US13116590
申请日：2011-05-26
申请人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
发明人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
IPC分类号： G11C11/00
CPC分类号： H01L45/085 , G11C13/0026 , G11C13/0069 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2472 , H01L45/1233 , H01L45/1266 , H01L45/145
摘要： A resistance random access change memory device includes: a memory cell array in which plural memory cells having current paths with series-connected access transistors and variable resistive elements are two-dimensionally arranged; plural bit lines that connect one ends of the current paths; plural source lines that connect the other ends of the current paths; and plural word lines that control conduction and non-conduction of the access transistors, wherein bit line contacts are shared between two memory cells to which the word lines are adjacently provided, and pairs of memory cells are formed, all of the pairs of memory cells connected to the adjacent two bit lines are connected to the corresponding source lines via individual source line contacts, and the source lines are formed by a wiring layer upper than that of the bit lines with a larger pitch than that of the bit lines.
摘要翻译：电阻随机存取改变存储器件包括：存储单元阵列，其中具有串联连接的存取晶体管和可变电阻元件的电流路径的多个存储单元被二维布置; 连接当前路径的一端的多个位线; 连接当前路径的另一端的多条源极线; 以及控制存取晶体管的导通和非导通的多个字线，其中位线接触在相邻设置有字线的两个存储单元之间共享，并且形成存储单元对，所有存储单元对连接到相邻的两条位线通过各个源极线接触连接到相应的源极线，并且源极线由比位线的间距高于位线的布线层形成。

6. 发明授权

US08559253B2 Variable-resistance memory device with charge sharing that discharges pre-charge voltage of a selected bit line to share charge with unselected bit lines 失效
标题翻译：具有电荷共享的可变电阻存储器件，其放电所选位线的预充电电压以与未选择的位线共享电荷
公开(公告)号：US08559253B2
公开(公告)日：2013-10-15
申请号：US13067933
申请日：2011-07-08
申请人： Makoto Kitagawa , Hiroshi Yoshihara
发明人： Makoto Kitagawa , Hiroshi Yoshihara
IPC分类号： G11C7/00
CPC分类号： G11C13/0009 , G11C7/12 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0073 , G11C2213/56 , G11C2213/79
摘要： A variable-resistance memory device that includes a memory-cell array employing a plurality of memory cells each including a storage element and an access transistor. The storage element has a resistance varying in accordance with the direction of a voltage applied to the storage element and the access transistor is connected in series to the storage element between a bit line and a source line. A voltage supplying circuit sets a read voltage used for reading out the resistance of the storage element on a selected bit line connected to the memory cell serving as a read object in an operation to supply the read voltage to the selected bit line.
摘要翻译：一种可变电阻存储器件，包括采用包括存储元件和存取晶体管的多个存储单元的存储单元阵列。存储元件具有根据施加到存储元件的电压的方向而变化的电阻，并且存取晶体管与位线和源极线之间的存储元件串联连接。电压提供电路在将读取电压提供给所选位线的操作中设置用于读出连接到用作读取对象的存储单元的选定位线上的存储元件的电阻的读取电压。

7. 发明申请

US20110110142A1 Memory device and method of reading memory device 失效
标题翻译：存储器件和读取存储器件的方法
公开(公告)号：US20110110142A1
公开(公告)日：2011-05-12
申请号：US12923978
申请日：2010-10-19
申请人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
发明人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
IPC分类号： G11C7/08 , G11C11/21
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0061 , G11C2013/0054 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.
摘要翻译：存储装置包括：存储单元，其中两个电极之间的电荷放电速率根据所存储信息的逻辑而不同; 读出放大器，通过将存储单元的一个电极与其连接的布线的放电电位与参考电位进行比较来检测信息的逻辑; 以及复制电路，其具有仿真存储器单元的复制单元，并且根据复制单元的放电速率来控制读出放大器的感测时序。

8. 发明授权

US4022808A Process for the production of alkylene glycol ether of organic carboxylic acid 失效
标题翻译：制备有机羧酸亚烷基二醇醚的方法
公开(公告)号：US4022808A
公开(公告)日：1977-05-10
申请号：US524156
申请日：1974-11-15
申请人： Hiroshi Yoshihara , Takashi Tobita , Ryoichi Tomizawa , Kunio Ishikawa
发明人： Hiroshi Yoshihara , Takashi Tobita , Ryoichi Tomizawa , Kunio Ishikawa
IPC分类号： B01J31/02 , B01J31/12 , B01J31/14 , B01J31/18 , B01J31/24 , B01J31/26 , C08G65/12 , C08G65/26 , C09F5/08 , C09F7/10
CPC分类号： C08G65/2615 , B01J31/0212 , B01J31/0234 , B01J31/122 , B01J31/143 , B01J31/26 , C08G65/12
摘要： A process for the production of an alkylene glycol ether ester of organic acid which comprises reacting an alkylene oxide and an ester of organic carboxylic acid by using a catalytic amount of a basic catalyst selected from the group of halogenides consisting of zinc, aluminum, titanium, tin and iron, and organometallic compounds of zinc, aluminum, titanium, tin and iron.
摘要翻译：一种制备有机酸的亚烷基二醇醚酯的方法，其包括使用催化量的选自以下的碱金属催化剂使烯化氧与有机羧酸的酯反应：选自由锌，铝，钛，锡和铁，以及锌，铝，钛，锡和铁的有机金属化合物。

9. 发明申请

US20100051573A1 Integrally Molded Hinge Cap 审中-公开
标题翻译：整体成型铰链帽
公开(公告)号：US20100051573A1
公开(公告)日：2010-03-04
申请号：US12304671
申请日：2006-10-17
申请人： Hiroshi Yoshihara
发明人： Hiroshi Yoshihara
IPC分类号： B65D41/00 , B65D43/16
CPC分类号： B65D47/0814
摘要： A hinge cap (10) fitted to a slant opening wall (26), which is provided around the opening of a hinge cap body (12), by means of two adjacently standing slant plugs (30, 32) of a lid (12). Because the slant plugs (30, 32) of the lid (12) are fitted by a large contact area to the slant opening wall (26) of the hinge cap body (12), the slant plugs can be applied to the hinge cap (10) having a relatively large area. Also, with the lid extended, the wall height of the slant outer plug (32) decreases as it approaches the rotation axis of the lid (12) and the wall height of the slant inner plug (30) decreases as it is away from the rotating shaft of the lid (12), so that the lid (12) can be smoothly rotated and opened in pressing and opening operation.
摘要翻译：铰链盖（10），其通过盖（12）的两个相邻的倾斜塞（30,32）安装在倾斜开口壁（26）上，所述倾斜开口壁（26）围绕铰链盖主体（12）的开口设置，。由于盖（12）的倾斜塞子（30,32）通过大的接触区域安装到铰链盖主体（12）的倾斜开口壁（26）上，所以可以将倾斜塞子施加到铰链盖（ 10）具有相对较大的面积。此外，当盖延伸时，倾斜的外部塞子（32）的壁高度随着其接近盖子（12）的旋转轴线而减小，并且斜内部塞子（30）的壁高度随着其远离盖（12）的旋转轴，使得盖（12）能够在按压和打开操作中平稳地旋转和打开。

10. 发明申请

US20080304343A1 METHOD AND APPARATUS FOR TESTING A CIRCUIT 失效
标题翻译：用于测试电路的方法和装置
公开(公告)号：US20080304343A1
公开(公告)日：2008-12-11
申请号：US11758743
申请日：2007-06-06
申请人： Hiroshi Yoshihara
发明人： Hiroshi Yoshihara
IPC分类号： G11C29/00
CPC分类号： G11C29/36 , G11C2029/0405 , G11C2029/3602
摘要： A system and method for testing a memory array are disclosed which may include establishing a stored data vector, including a plurality of data bits, within at least one circuit; applying one or more logical operations on the stored data vector to generate a succession of original data vectors at the at least one circuit; transmitting the succession of original data vectors through a memory array to provide a succession of exercised data vectors; comparing the succession of exercised data vectors to the succession of respective original data vectors; and determining whether the memory array passes or fails based on the comparing step.
摘要翻译：公开了一种用于测试存储器阵列的系统和方法，其可以包括在至少一个电路内建立包括多个数据位的存储数据向量; 对所存储的数据向量应用一个或多个逻辑运算，以在所述至少一个电路上产生一系列原始数据向量; 通过存储器阵列传送原始数据向量的继承以提供一系列行使的数据向量; 将行使的数据向量的继承与相应原始数据向量的连续进行比较; 以及基于所述比较步骤来确定所述存储器阵列是否通过或失败。

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