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    • 4. 发明授权
    • Semiconductor integrated circuit and layout method thereof
    • 半导体集成电路及其布局方法
    • US6130485A
    • 2000-10-10
    • US210673
    • 1998-12-14
    • Masahiko Hirai
    • Masahiko Hirai
    • H01L27/04H01L21/82H01L21/822H01L27/02H01L23/48H01L23/52H01L29/40
    • H01L27/0207
    • A pad block is provided with a pad, an output buffer circuit and an internal circuit. The region between the internal circuit and the output buffer circuit serves as an element arrangement forbidden region. In this region, the internal circuit and the output buffer circuit are connected to each other by, for example, a polysilicon layer. The internal circuit is connected to a circuit formed in an internal region of a chip by using at least two wiring layers passing the element arrangement forbidden region. By laying out the wiring connecting the internal circuit within the pad block to the circuit in the internal region of the chip in the element arrangement forbidden region provided within the pad block, it is possible to reduce a space necessary for wiring and thereby to realize a highly integrated device.
    • 焊盘块设有焊盘,输出缓冲电路和内部电路。 内部电路和输出缓冲电路之间的区域用作禁止区域的元件布置。 在该区域中,内部电路和输出缓冲电路通过例如多晶硅层彼此连接。 内部电路通过使用穿过元件布置禁区的至少两个布线层连接到形成在芯片的内部区域中的电路。 通过布置将焊盘块内的内部电路连接到设置在焊盘块内的元件布置禁止区域中的芯片的内部区域中的电路,可以减少布线所需的空间,从而实现 高度集成的设备。