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1. 发明授权

US08346828B2 System and method for storing numbers in first and second formats in a register file 有权
标题翻译：用于在寄存器文件中存储第一和第二格式的数字的系统和方法
公开(公告)号：US08346828B2
公开(公告)日：2013-01-01
申请号：US12250935
申请日：2008-10-14
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F5/00
CPC分类号： G06F9/30025 , G06F7/57 , G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/30192 , G06F2207/3824
摘要： A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
摘要翻译：提供了一种用于将数字存储在寄存器文件中的系统和方法。系统和方法以浮点数计算单位和不支持浮点数的计算单位共享的寄存器文件中存储双精度格式的单精度数字。

2. 发明授权

US08032854B2 3-stack floorplan for floating point unit 有权
标题翻译：浮动单元的3层平面布置图
公开(公告)号：US08032854B2
公开(公告)日：2011-10-04
申请号：US12201092
申请日：2008-08-29
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
摘要翻译：用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。

3. 发明申请

US20100058266A1 3-Stack Floorplan for Floating Point Unit 有权
标题翻译：浮点单元3堆叠平面图
公开(公告)号：US20100058266A1
公开(公告)日：2010-03-04
申请号：US12201092
申请日：2008-08-29
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
摘要翻译：用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。

4. 发明申请

US20100095099A1 SYSTEM AND METHOD FOR STORING NUMBERS IN FIRST AND SECOND FORMATS IN A REGISTER FILE 有权
标题翻译：用于在寄存器文件中存储第一和第二格式的数字的系统和方法
公开(公告)号：US20100095099A1
公开(公告)日：2010-04-15
申请号：US12250935
申请日：2008-10-14
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F9/302 , G06F9/312 , G06F7/38
CPC分类号： G06F9/30025 , G06F7/57 , G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/30192 , G06F2207/3824
摘要： A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
摘要翻译：提供了一种用于将数字存储在寄存器文件中的系统和方法。系统和方法以浮点数计算单位和不支持浮点数的计算单位共享的寄存器文件中存储双精度格式的单精度数字。

5. 发明授权

US08407275B2 Fast floating point compare with slower backup for corner cases 有权
标题翻译：快速浮点与较慢的备份角落比较
公开(公告)号：US08407275B2
公开(公告)日：2013-03-26
申请号：US12255968
申请日：2008-10-22
申请人： Maarten J. Boersma , Michael Kroener , Silvia M. Mueller , Jochen Preiss
发明人： Maarten J. Boersma , Michael Kroener , Silvia M. Mueller , Jochen Preiss
IPC分类号： G06F7/02
CPC分类号： G06F9/30021 , G06F9/30025
摘要： A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail.
摘要翻译：浮点处理器单元通过比较整数格式的两个操作数来执行具有相同或不同精度的两个操作数的浮点比较指令，这显着地加快了浮点比较指令的执行。浮点处理器现在对于几乎大多数操作数情况（例如，所有情况的99％），至少执行两倍快或更快（例如，现有技术中的两个时钟周期而不是五个时钟周期）的浮点比较指令。只有罕见的角落情况需要在其中一个操作数上进行额外的操作，因此需要额外的执行周期，因为整数比较操作将不适用于这些角色。这是由于一个操作数是非正规化表示中的单精度子正规数（即，具有两个表示），另一个操作数处于SP子正常范围，使得整数比较操作将失败。

6. 发明申请

US20100100713A1 FAST FLOATING POINT COMPARE WITH SLOWER BACKUP FOR CORNER CASES 有权
标题翻译：快速浮动点与用于角膜的SLOWER BACKUP比较
公开(公告)号：US20100100713A1
公开(公告)日：2010-04-22
申请号：US12255968
申请日：2008-10-22
申请人： Maarten J. Boersma , Michael Kroener , Silvia M. Meuller , Jochen Preiss
发明人： Maarten J. Boersma , Michael Kroener , Silvia M. Meuller , Jochen Preiss
IPC分类号： G06F9/302
CPC分类号： G06F9/30021 , G06F9/30025
摘要： A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail.
摘要翻译：浮点处理器单元通过比较整数格式的两个操作数来执行具有相同或不同精度的两个操作数的浮点比较指令，这显着地加快了浮点比较指令的执行。浮点处理器现在对于几乎大多数操作数情况（例如，所有情况的99％），至少执行两倍快或更快（例如，现有技术中的两个时钟周期而不是五个时钟周期）的浮点比较指令。只有罕见的角落情况需要在其中一个操作数上进行额外的操作，因此需要额外的执行周期，因为整数比较操作将不适用于这些角色。这是由于一个操作数是非正规化表示中的单精度子正规数（即，具有两个表示），另一个操作数处于SP子正常范围，使得整数比较操作将失败。

7. 发明申请

US20110320512A1 Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection 失效
标题翻译：十进制浮点机制和乘法过程，无需导致零检测
公开(公告)号：US20110320512A1
公开(公告)日：2011-12-29
申请号：US12821648
申请日：2010-06-23
申请人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
发明人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
IPC分类号： G06F7/44 , G06F5/01
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format.
摘要翻译：具有系数机制而不产生前导零检测（LZD）的计算机中的固定和浮点计算的十进制乘法机制，其假设最终产品的长度为M + N个数字，并且基于该假设执行所有计算。将被截断的最低有效数字不再存储，而是保留为用于确定结果产品的粘性信息。一旦产品的计算完成，就使用基于在部分积累期间观察到的关键位的检查的最终检查来确定最终产品是真正的M + N个数字的长度，还是M + N-1个数字。如果后者是真实的，则采用校正最终产品转换来获得适当的结果。这消除了用于确定最终产品中有效数字数量的专用前导零检测硬件的需要。当产品的指数处于极端状态并且最终产品必须在给定格式的精度和范围内时，纠正性最终产品转移也会对产品系数进行调整。

8. 发明申请

US20060179100A1 System and method for performing floating point store folding 失效
标题翻译：执行浮点存储折叠的系统和方法
公开(公告)号：US20060179100A1
公开(公告)日：2006-08-10
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译：一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

9. 发明授权

US06694344B1 Examination of residues of data-conversions 失效
标题翻译：检查数据转换的残留
公开(公告)号：US06694344B1
公开(公告)日：2004-02-17
申请号：US09436851
申请日：1999-11-09
申请人： Guenter Gerwig , Juergen Haess , Michael Kroener , Erwin Pfeffer
发明人： Guenter Gerwig , Juergen Haess , Michael Kroener , Erwin Pfeffer
IPC分类号： G06F1100
CPC分类号： G06F11/085 , G06F7/72 , H03M7/02
摘要： A process is provided for monitoring the conversion of numerical values from a first to a second format, where before and after the conversion, the modulo residue of the corresponding numerical value is calculated and compared with the corresponding residue after the conversion. In this way it is possible to effect error-free monitoring of such a conversion, especially of computer data, without great hardware expenditure.
摘要翻译：提供了用于监视从第一格式到第二格式的数值的转换的过程，其中在转换之前和之后，计算相应数值的模余数并将其与转换后的相应残差进行比较。以这种方式，可以在没有很好的硬件支出的情况下，对这种转换，特别是计算机数据进行无差错监视。

10. 发明授权

US5478656A Cationic urea/formaldehyde resins, their preparation and their use in the paper industry 失效
标题翻译：阳离子脲/甲醛树脂，其制备及其在造纸工业中的应用
公开(公告)号：US5478656A
公开(公告)日：1995-12-26
申请号：US408408
申请日：1995-03-22
申请人： Klaus Flory , Andreas Stange , Michael Kroener , Norbert Sendhoff
发明人： Klaus Flory , Andreas Stange , Michael Kroener , Norbert Sendhoff
IPC分类号： C08G12/12 , C08G12/46 , D21H17/49 , D21H17/50 , B32B27/42
CPC分类号： C08G12/46 , Y10T428/31949 , Y10T428/31964
摘要： Cationic urea/formaldehyde resins are obtainable by condensing urea and formaldehyde in a molar ratio of from 1:1.5 to 1:3 in the presence of polymers which contain not less than 1 mol % of polymerized vinylamine units and have Fikentscher K values of from 5 to 300, in an amount of from 5 to 50 g per mole of urea in the end product, where the mixture is first a) precondensed at a pH of from 8 to 14, then acidified and b) condensed at a pH of from 1 to 5 until gel formation begins, c) then from 0.3 to 1.5 moles of formaldehyde are added per mole of urea used, d) post-condensation is carried out and e) the resin solution is subsequently neutralized. The resins thus obtained are used in papermaking as assistants for increasing the dry and wet strength of paper and result in less dulling of the whiteness of the paper.
摘要翻译：阳离子脲/甲醛树脂可以通过在含有不少于1摩尔％的聚合乙烯胺单元的聚合物存在下，以1:1.5至1:3的摩尔比冷凝脲和甲醛，并且具有5的Fikentscher K值至300，其量为最终产物中每摩尔尿素5至50g，其中混合物首先a）在8至14的pH下预缩合，然后酸化并b）在pH为1时冷凝至5，直到凝胶形成开始，c）然后每摩尔使用的尿素加入0.3至1.5摩尔的甲醛，d）进行后冷凝，e）随后中和树脂溶液。由此获得的树脂用于造纸中作为助剂以增加纸张的干湿强度，并且导致纸的白度较少的钝化。

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