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1. 发明专利

DE60041863D1 未知
公开(公告)号：DE60041863D1
公开(公告)日：2009-05-07
申请号：DE60041863
申请日：2000-06-30
申请人： MITSUBISHI MATERIAL SILICON , MITSUBISHI ELECTRIC CORP
发明人： TAKAMATSU M , KATAKURA T , IWAMATSU TOSHIAKI , NARUOKA HIDEKI
IPC分类号： H01L27/12 , H01L21/265 , H01L21/266 , H01L21/762 , H01L21/84 , H01L23/544
摘要： A manufacturing method of a SOI substrate (10) comprises the steps of: forming an oxide film (12) at cross-sectional both main surfaces and cross-sectional both end surfaces of a silicon substrate (11); forming a resist layer (13) on the oxide film (12) at cross-sectional both end surfaces of the substrate (11); and removing the oxide film (12) at those portions which are left from the covering of the resist layer (13), to thereby expose the both main surfaces of the substrate (11). Next, the resist layer (13) is removed to thereby leave the oxide film (12) at the both end surfaces of the substrate (11); and oxygen ions (I) are dosed into the substrate (11) from one of the exposed both main surfaces, followed by an anneal processing to thereby form an oxide layer (14) in a region at a predetermined depth from the one main surface of the substrate (11). The oxide film (12) left on the both end surfaces of the substrate (11) is then removed.

2. 发明公开

EP1122788A4 SOI SUBSTRATE, METHOD OF MANUFACTURE THEREOF, AND SEMICONDUCTOR DEVICE USING SOI SUBSTRATE 有权
标题翻译： SOI SUBSTRAT，HERSTELLUNGSVERFAHREN，DAS SOI SUBSTRAT VERWENDENDE HALBLEITERBAUELEMENT
公开(公告)号：EP1122788A4
公开(公告)日：2006-05-17
申请号：EP00942438
申请日：2000-06-30
申请人： MITSUBISHI MATERIAL SILICON , MITSUBISHI ELECTRIC CORP
发明人： TAKAMATSU M , KATAKURA T , IWAMATSU TOSHIAKI , NARUOKA HIDEKI
IPC分类号： H01L21/762 , H01L21/265 , H01L21/266 , H01L21/84 , H01L23/544 , H01L27/12
CPC分类号： H01L21/76243 , H01L21/26533 , H01L21/266 , H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L21/84 , H01L23/544 , H01L27/1203 , H01L2223/54406 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： In manufacturing an SOI substrate (10), oxide film (12) is formed on both sides and both edges of a silicon substrate (11), resist (13) is applied to the oxide film (12) on both edges of the substrate (11), and portions of the oxide film (12), which are not covered with the resist (13), are removed to expose both sides of the substrate (11). The resist (13) is then removed with the oxide film (12) remaining on both edges. Oxygen ions (I) are injected through one side of the substrate (11) and annealed to form a buried silicon oxide (14) in a region at a predetermined depth from the one side of the substrate (11). The oxide film (12) remaining on both edges of the substrate (11) is removed.
摘要翻译： SOI衬底（10）的制造方法包括以下步骤：在硅衬底（11）的两个主表面和两个两端面的横截面上形成氧化膜（12）; 在所述基板（11）的两个端面的横截面上在所述氧化物膜（12）上形成抗蚀剂层（13）; 以及在从抗蚀剂层（13）的覆盖层留下的部分去除氧化膜（12），从而露出基板（11）的两个主表面。接下来，除去抗蚀剂层（13），从而在基板（11）的两个端面处留下氧化膜（12）。和氧离子（I）从暴露的两个主表面中的一个喷射到衬底（11）中，随后进行退火处理，从而在与主体表面的一个主表面预定深度的区域中形成氧化物层（14）基板（11）。然后去除留在基板（11）的两个端面上的氧化膜（12）。

3. 发明专利

FR2797523A1 Semiconductor substrate inspection process, for detecting internal flaws in an SOI substrate semiconductor layer, comprises etching a dielectric layer through a perforated thermally oxidized or heat treated semiconductor layer 未知
公开(公告)号：FR2797523A1
公开(公告)日：2001-02-16
申请号：FR0009956
申请日：2000-07-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： NARUOKA HIDEKI
IPC分类号： G01N1/32 , G01N1/28 , G01N33/00 , H01L21/66 , H01L27/12
摘要： SOI substrate inspection, by etching a dielectric layer (20) through a perforated thermally oxidized or heat treated semiconductor layer (10), is new. A semiconductor substrate inspection process comprises subjecting a substrate (1), comprising a dielectric layer (20) bearing a semiconductor layer (10) which has a bare surface (10S) on the opposite side from the dielectric layer, to either (a) thermal oxidation of the bare semiconductor layer surface to form a thermal oxide film, etching of the thermal oxide film and etching of the dielectric layer through the perforated thermal oxide film; or (b) thermal treatment of the semiconductor substrate, isotropic etching of the bare semiconductor layer surface and etching of the dielectric layer through the perforated semiconductor layer.

4. 发明专利

DE19837646A1 SOI semiconductor substrate production by SIMOX method 未知
公开(公告)号：DE19837646A1
公开(公告)日：1999-07-15
申请号：DE19837646
申请日：1998-08-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： YOSHIDA YOSHIKO , NARUOKA HIDEKI , KIMURA YASUHIRO , YAMAGUCHI YASUO , IWAMATSU TOSHIAKI , HIRANO YUUICHI
IPC分类号： H01L21/265 , H01L21/02 , H01L21/3105 , H01L21/3115 , H01L21/762 , H01L27/12 , H01L21/84
摘要： A silicon-on-insulator (SOI) semiconductor substrate, produced by a SIMOX (separation by implanted oxygen) method and having a central active region and a stacked arrangement of a buried oxide layer (2) and an SOI layer (1), is processed by silicon ion implantation in its peripheral and side portions to eliminate the buried oxide layer from these portions. Independent claims are also included for the following: (i) processing of a semiconductor substrate, having an active region in a central portion, by covering the peripheral and side portions of the substrate (3) with an insulating layer, implanting oxygen ions at the substrate side to form a buried oxide layer (2) and an SOI layer (1) by a SIMOX method and then removing the insulating layer to form an SOI substrate; and (ii) a similar processing method involving implantation of oxygen ions at the side over the entire substrate surface, selective implantation of oxygen ions into the substrate peripheral and side portions side and then heat treatment.

5. 发明专利

FR2797523B1 未知
公开(公告)号：FR2797523B1
公开(公告)日：2003-08-15
申请号：FR0009956
申请日：2000-07-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： NARUOKA HIDEKI
IPC分类号： G01N1/32 , G01N1/28 , G01N33/00 , H01L21/66 , H01L27/12
摘要： An SOI substrate having a silicon layer formed on an embedded oxide layer is prepared at a step ST11. An exposed surface of the silicon layer is thermally oxidized for forming a thermal oxide film at a step ST12. The thermal oxide film, enclosing a defect in the silicon layer, is formed in a shape on or to which the defect is reflected or transferred. At this time, thermal oxidation is so executed that the transferred part of the thermal oxide film is in contact with the embedded oxide layer. The SOI substrate is dipped in a hydrofluoric acid solution at a step ST13. Thus, the thermal oxide film is removed while the embedded oxide layer is eroded through the part in contact with the thermal oxide film. According to this inspection method ST10, the defect is reliably transferred to the embedded oxide layer through the thermal oxidation step ST12, whereby it is possible to evaluate an inner defect undetectable/unevaluative by a conventional inspection method. Thus, the defect of the silicon layer is inspected/evaluated for obtaining an SOI substrate of high quality and improving the manufacturing yield of a semiconductor device.

6. 发明专利

DE19837646B4 未知
公开(公告)号：DE19837646B4
公开(公告)日：2004-05-06
申请号：DE19837646
申请日：1998-08-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： YOSHIDA YOSHIKO , NARUOKA HIDEKI , KIMURA YASUHIRO , YAMAGUCHI YASUO , IWAMATSU TOSHIAKI , HIRANO YUUICHI
IPC分类号： H01L21/265 , H01L21/02 , H01L21/3105 , H01L21/3115 , H01L21/762 , H01L27/12 , H01L21/84
摘要： A semiconductor substrate that prevents formation of particles from an edge part of the substrate. The substrate contains an on-substrate oxide film and an SOI layer stacked on the oxide film. A molten layer is formed on the edge part of the on-substrate oxide film and the SOI layer by mixing the SOI layer and the on-substrate oxide film to cover the edge part. An epitaxial layer may also be formed on the edge part of the on-substrate oxide film and the SOI layer to cover the edge part.

7. 发明专利

FR2818011A1 未知
公开(公告)号：FR2818011A1
公开(公告)日：2002-06-14
申请号：FR0114779
申请日：2001-11-15
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWAMATSU TOSHIAKI , IPPOSHI TAKASHI , NARUOKA HIDEKI , HATTORI NOBUYOSHI , MAEGAWA SHIGETO , YAMAGUCHI YASUO , MATSUMOTO TAKUJI
IPC分类号： H01L21/76 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/12 , H01L29/45 , H01L29/786 , H01L27/088
摘要： To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST 21 ), a polysilicon film (PS 21 ) is selectively provided on the trench isolation oxide film (ST 21 ), a silicon layer (S 22 ) is provided on the polysilicon film (PS 21 ), and a side wall spacer (SW 2 ) is provided on a side surface of the polysilicon film (PS 21 ). The polysilicon film (PS 21 ) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR 11 ) and an N-type well region (WR 12 ) in an SOI layer 3 across the two well regions.

8. 发明专利

DE10155452A1 未知
公开(公告)号：DE10155452A1
公开(公告)日：2002-05-29
申请号：DE10155452
申请日：2001-11-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWAMATSU TOSHIAKI , IPPOSHI TAKASHI , NARUOKA HIDEKI , HATTORI NOBUYOSHI , MAEGAWA SHIGETO , YAMAGUCHI YASUO , MATSUMOTO TAKUJI
IPC分类号： H01L21/76 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/12 , H01L29/45 , H01L29/786
摘要： To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST 21 ), a polysilicon film (PS 21 ) is selectively provided on the trench isolation oxide film (ST 21 ), a silicon layer (S 22 ) is provided on the polysilicon film (PS 21 ), and a side wall spacer (SW 2 ) is provided on a side surface of the polysilicon film (PS 21 ). The polysilicon film (PS 21 ) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR 11 ) and an N-type well region (WR 12 ) in an SOI layer 3 across the two well regions.

9. 发明专利

JP2003188223A METHOD FOR MAKING CRYSTAL DEFECT OBVIOUS, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE FOR EVALUATION, METHOD FOR EVALUATING CRYSTAL DEFECT, AND SEMICONDUCTOR DEVICE FOR EVALUATION 审中-公开
公开(公告)号：JP2003188223A
公开(公告)日：2003-07-04
申请号：JP2001386208
申请日：2001-12-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： NARUOKA HIDEKI
IPC分类号： H01L21/66 , H01L23/544
摘要： PROBLEM TO BE SOLVED: To obtain an evaluation method of crystal defects for evaluating the crystal defects that are generated in a thin-film SOI layer and a thin-film surface layer through inline inspection. SOLUTION: In the evaluation region of an SOI layer 3, a silicide region 8 corresponding to a crystal defect generated in the SOI layer 3 is formed. In the silicide region 8, a metal element contained in a transition layer 10 is diffused into the SOI layer 3 through heat treatment, and is subjected to gettering by the crystal defects for silicide. Laser beams are irradiated inside the evaluation region through the transition layer 10 and a silicon oxide film 6. The evaluation region is scanned by laser beams, and at the same time, a current flowing between the first and second probes is detected by an ammeter, thus evaluating the crystal defects in the evaluation region. COPYRIGHT: (C)2003,JPO

10. 发明专利

JP2003031779A Method for manufacturing soi wafer 审中-公开
标题翻译： SOI WAFER制造方法
公开(公告)号：JP2003031779A
公开(公告)日：2003-01-31
申请号：JP2001213648
申请日：2001-07-13
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NARUOKA HIDEKI , HATTORI NOBUMI , YAMAMOTO HIDEKAZU
IPC分类号： H01L21/683 , H01L21/00 , H01L21/02 , H01L21/762 , H01L27/12 , H01L21/68
CPC分类号： H01L21/67092 , H01L21/76251 , Y10S414/138
摘要： PROBLEM TO BE SOLVED: To obtain a method for manufacturing an SOI wafer capable of avoiding occurrence of a damage of a support substrate for causing a thermal crack of the wafer or a slip dislocation.
SOLUTION: A boat 4 has a recess 5 formed to support a laminated wafer 50. The recess 5 has a first side face 5a, a first bottom 5b, a second side face 5c, a second bottom 5d and a third side face 5e. As seen from an upper surface of the boat 4, the bottom 5d exists at a deeper position than the bottom 5b. The wafer 50 is brought at the side face of a silicon wafer 2 into contact with the bottom 5b of the recess 5, and charged in the boat 4 in a state in which the side face of a silicon wafer 1 is not brought into contact with the bottom 5d of the recess 5. A second main surface 2b of the wafer 2 is brought into contact with the side face 5a of the recess 5, and a second main surface 1a of the wafer 1 is brought into contact with a third side face 5e of the recess 5.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：获得能够避免发生用于引起晶片热裂纹或滑移位错的支撑基板损坏的SOI晶片的制造方法。解决方案：船4具有形成为支撑层压晶片50的凹部5.凹部5具有第一侧面5a，第一底部5b，第二侧面5c，第二底部5d和第三侧面5e。从舟皿4的上表面看，底部5d位于比底部5b更深的位置。晶片50被带到硅晶片2的侧面与凹部5的底部5b接触，并且在硅晶片1的侧面不与其接触的状态下被装载在舟皿4中凹部5的底部5d。晶片2的第二主表面2b与凹部5的侧面5a接触，晶片1的第二主表面1a与第三侧面 5e的凹部5。

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