专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH04171979A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04171979A
公开(公告)日：1992-06-19
申请号：JP30154390
申请日：1990-11-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUDA KAKUTAROU
IPC分类号： H01L27/082 , H01L21/8222 , H01L21/8229 , H01L27/102 , H01L27/105 , H01L29/08
摘要： PURPOSE:To obtain a semiconductor device which does not produce a difference in level between a first region and a second region on the surface of an epitaxial layer and which can make the film thickness of said layer different between both regions by a method wherein the epitaxial layer has a surface whose height is the same in the first and second regions and in which a U-shaped stepped part has been formed in the boundary part between both regions. CONSTITUTION:The surface of a p semiconductor substrate 11 is formed to be high in a memory cell region and to be low in a peripheral circuit region. An n type buried semiconductor layer 12 whose thickness is substantially uniform and whose impurity concentration is high is formed on the surface of the p semiconductor substrate 11. Consequently, also the surface of the buried semiconductor layer 12 has a difference in level between the memory cell region and the peripheral circuit region. An n type epitaxial layer 13 whose impurity concentration is low is formed on the surface of the n type buried semiconductor layer 12. Since the surface of the epitaxial layer 13 is formed to be of the same height at the memory region and the peripheral circuit region, the film thickness E1 of the epitaxial layer 13 is thin in the memory cell region and the peripheral circuit region id thick at E2. A U-shaped stepped part 16 is formed in the boundary part between the memory cell region and the peripheral circuit region on the surface of the epitaxial layer 13.

2. 发明专利

JPH02208949A SEMICONDUCTOR MANUFACTURING DEVICE 失效
公开(公告)号：JPH02208949A
公开(公告)日：1990-08-20
申请号：JP3024989
申请日：1989-02-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAKAMURA HIROSHI , OMORI TOSHIAKI , SUDA KAKUTAROU
IPC分类号： G01R31/26 , H01L21/66
摘要： PURPOSE:To perform reliably the judgement of the good or bad of data in the stage in the middle of inspection by a method wherein inspecting machines for semiconductor wafers are provided with read means, the sampling numbers of the waters and inspection information are prepared and history data is stored. CONSTITUTION:A prescribed treatment is performed on semiconductor wafers 1 and thereafter, the wafers 1 are housed in a cassette 3. Moreover, the wafers 1 are carried in inspecting machines (a first inspecting machine, a second inspecting machine to a (n)th inspecting machine) A1, A2 to An to correspond to processes and an inspection of pattern defect and the like is performed by a wafer defect inspecting device 60 of the machines. Here, the wafers 1 are automatically read the wafer numbers of their numbering parts 2 by wafer number detectors 7 during the transfer to the device 60. Then, inspection information on the result of the pattern defect inspection performed by the device 60 and the water numbers from the detectors 7, which are shown in such a way as to correspond to 1:1, is prepared and is stored in a main computor 8 through a communication line 12. This process is repeated and when wafer numbers identical with the wafer numbers stored in the computor 8 are detected by the detectors 7, the good or bad of data is reliably judged.

3. 发明专利

JPH07161855A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07161855A
公开(公告)日：1995-06-23
申请号：JP30936293
申请日：1993-12-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUDA KAKUTAROU
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L29/10 , H01L29/73 , H01L29/732
摘要： PURPOSE:To lessen the insulation capacitance between an emitter electrode and a base layer by interposing a first insulating layer, a semiconductor layer, and a second insulating layer between the emitter electrode and a base layer. CONSTITUTION:A gate oxide film 17a, a lower layer polycrystalline silicon film 18a, an oxide film 19a, and a sidewall oxide film 20a are interposed between a p-type base layer 9 and an upper polycrystalline silicon film 21a constituting an emitter electrode. Hereby, the upper polycrystalline silicon film 21a and the p-type base layer 9 are insulated from each other by the gate oxide film 17a, the lower polycrystalline silicon film 18a, and the sidewall film 20a, or the oxide film 19a. As a result, the insulation capacitance between the upper polycrystalline silicon film 21a and the p-type base layer 9 becomes small. Hereby, the parasitic capacitance between the emitter and the base becomes small. Accordingly, the drop of the operation speed of a bipolar transistor can be prevented effectively.

4. 发明专利

JPH04323832A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04323832A
公开(公告)日：1992-11-13
申请号：JP12261691
申请日：1991-04-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUDA KAKUTAROU , KINOSHITA YASUSHI , IKEDA TATSUHIKO
IPC分类号： H01L21/76 , H01L21/331 , H01L29/205 , H01L29/73 , H01L29/732
摘要： PURPOSE:To provide electrical isolation from an adjacent element and reduce steps between a base electrode and emitter/collector electrodes in a hetero bipolar transistor having a base layer which has a narrower energy band gap than a collector layer and an emitter layer. CONSTITUTION:An emitter layer 5 is also formed on an epitaxial layer 3 other than a base layer forming region. Trench-type element isolation layers 10 which reach a semiconductor substrate 1 from the surfaces of the emitter layers 5 are formed and, further, a trench-type collector-base isolation layer 11 which reaches the epitaxial layer 3 from the surface of the emitter layer 5 in a region which includes at least a part of the base layer 4.

5. 发明专利

JPH03200335A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03200335A
公开(公告)日：1991-09-02
申请号：JP34113689
申请日：1989-12-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUDA KAKUTAROU
IPC分类号： H01L21/76 , H01L21/322
摘要： PURPOSE:To obtain a high gettering effect independent of the oxygen density of a substrate and improve the yield of products by providing a region other than an element forming region with a plurality of narrowly spaced groove type separation patterns and absorbing a thermal stress generated in an element separation region into the groove type separation patterns. CONSTITUTION:An element forming region 30 composed of elements 5 and a groove type element separation region 61 is formed on a semiconductor substrate 1. Groove type separation patterns 60 like narrowly spaced square stripes are formed around the element forming region 30. Generally, since the narrower spacings between the adjacent grooves are, the more crystal defects tend to be generated in the groove type separation patterns 60 formed on the surface of the semiconductor substrate 1, the crystal defects 7 are induced in the neighborhood of the narrowly spaced groove type separation patterns 60 formed on a region other than the element forming region 30. The concentration of the crystal detects 7 is the neighborhood of the narrowly spaced groove type separation patterns 60 relieves a thermal stress generated in the element forming region 30 to make it a nondefective region. Thus, a high gettering effect can be obtained and the yield of products can be improved.

6. 发明专利

JPH02226742A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02226742A
公开(公告)日：1990-09-10
申请号：JP4701589
申请日：1989-02-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUDA KAKUTAROU
IPC分类号： H01L21/76 , H01L21/31
摘要： PURPOSE:To flatten the surface of a polycrystalline silicon film, with which a deep groove is filled, by a method wherein the film is subjected to selective oxidation treatment up to a depth lower than the surface of a semiconductor substrate. CONSTITUTION:In a state that the deposition thickness of a polycrystalline silicon film 14, with which a deep groove G1 covered with an oxide film 12b and a nitride film 13 is filled, is set in a degree that the lower end part of a recess G2 remaining on the surface of the central part of the groove G1 is positioned higher than the surface of the film 13, this film 14 is selectively subjected to oxidation treatment up to a depth lower than the surface of a semiconductor substrate 11 and an oxide film 12c is formed. Thereby, an interface 15a between the film 12c and the unoxidized film 14 can be flattened vary easily and moreover, by removing the film 12c, the flattened surface 15b of the film 14 can be exposed to the upper part of the interior of the groove G1 leaving a space part 16 of a prescribed depth.

7. 发明专利

JPH01129439A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01129439A
公开(公告)日：1989-05-22
申请号：JP28995487
申请日：1987-11-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUDA KAKUTAROU
IPC分类号： H01L21/76 , H01L21/31
摘要： PURPOSE:To form excellent trench isolation structure, and to improve performance by applying a crystalline layer or an amorphous layer onto the whole surface of the inwall of a trench, oxidizing said crystalline layer or amorphous layer through thermal oxidation, changing the layer into an oxide layer and burying said trench so as to cross and cover one main surface of a substrate. CONSTITUTION:A trench 4 is formed in a substrate 1 through a conventional process. A mask layer 2 on one main surface of the substrate 1 is removed, and an oxidation- resistant layer 10 such as an silicon oxide film is applied onto the whole surface in specified film thickness through a CVD method, etc. A polycrystalline silicon layer 11 is applied onto the whole surface on the layer 10 in predetermined film thickness through the CVD method, etc. The polycrystalline silicon layer 11 is oxidized through thermal oxidation, thus changing the layer 11 into an oxide layer 13 unified with the oxidation-resistant layer 10, then burying the inside of the trench 4. The upper section of the oxide layer 13 is spin-coated with a resist 7 for flattening, reactive ions having approximately the same etching rate as the resist are selected, and the resist 7 for flattening and the oxide layer 13 are removed continuously through etch- back through an RIE method, etc. One main surface of the substrate 1 is brought to an exposed state, thus leaving the oxide layer 13 in the trench 4.

8. 发明专利

JPS63237442A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63237442A
公开(公告)日：1988-10-03
申请号：JP7222587
申请日：1987-03-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： YANAGI MOTONORI , NISHIKAWA KIICHI , SUDA KAKUTAROU
IPC分类号： H01L21/3205
摘要： PURPOSE:To prevent a disconnection, a constriction or the like of a wiring part at a connecting part by a method wherein a conductive part for contact use is first formed selectively on an active region in order to connect the active region to an upper-layer wiring part to be formed later and, after that, an interlayer insulating film is formed. CONSTITUTION:An aluminum film 10 at a part where photosensitive coated films 9 are not formed is removed by an anisotropic etching method or the like, and contact aluminum parts 10 are formed. After that, a first insulating film 6 is formed in such a way that its height is about 1.5 times as high as the contact aluminum parts 10; the upper face of the first interlayer insulating film 6 is etched by an etching-back method or the like until the tip part of the contact aluminum parts 10 is exposed. Then, an aluminum film is formed on the upper part of the first interlayer insulating film 6 and the contact aluminum parts 10 by a sputtering method or the like; after the aluminum film has been patterned, an aluminum wiring part 5 is formed. Furthermore, a second interlayer insulating film 8 is formed on the aluminum wiring part 5. By this setup, source-drain regions 4 can be connected electrically to the aluminum wiring part 5 on it surely.

9. 发明专利

JPS62249471A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62249471A
公开(公告)日：1987-10-30
申请号：JP9512386
申请日：1986-04-22
申请人： MITSUBISHI ELECTRIC CORP
发明人： TAKAHASHI TAKETO , KINOSHITA YASUSHI , SUDA KAKUTAROU , NISHIKAWA KIICHI
IPC分类号： H01L21/768 , H01L21/822 , H01L27/04
摘要： PURPOSE:To form a resistance region with a very high resistance value uniformly and facilitate high integrity of a device by a method wherein a part of a layer insulating film which has a crystalline structure and separates different wirings is made to be amorphous by ion implantation of impurity. CONSTITUTION:A layer insulating film 7 is formed on 1st layer wirings 6 formed on an insulating film 3 by predetermined processes. Then optional impurity is implanted by ion implantation in a required region by using a mask such as a resist film. With this process, this part of the layer insulating film 7 is made to be amorphous and an amorphous layer resistance region 8 is formed. Then through-holes are formed. After that, 2nd layer wiring 9 is formed. Therefore, the amorphous layer resistance region 8 can function as a high resistance region and can also function as a through-hole.

10. 发明专利

JPS62247548A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62247548A
公开(公告)日：1987-10-28
申请号：JP9091486
申请日：1986-04-18
申请人： MITSUBISHI ELECTRIC CORP
发明人： KINOSHITA YASUSHI , SUDA KAKUTAROU , IKEDA TATSUHIKO , HIRAO TADASHI
IPC分类号： H01L21/768
摘要： PURPOSE:To obtain a semiconductor device that can select and connect any resistor formed in a substrate to a wiring layer without restrition due to a first layer of Al wiring by a method wherein a contact layer containing high melting point metal silicide is formed in connection to the resistor, and the resistor and a wiring layer are connected through the contact layer. CONSTITUTION:Enen when a first layer of Al wiring 8 is interconnected in what manner according to the design criterion, because an MoSi2 wiring 11 as a contact layer connected to a diffusion resistor 7 is formed under an interlayer insulating film 12, the degree of freedom of construction of a semiconductor device is enhanced with out limited by the wiring pitch of the first layer of Al wiring 8 and length of the diffusion resistor 7. Accordingly at a gate array and the like the slicing process is started at time when a resistance contact to the diffusion resistor 7 thereof is to be formed, and connection to the diffusion resistor 7 having the proper resistance value can be attained. Moreover even when the working electric power source voltage is changed, resistance to decide logic amplitude can be selected at the slicing process.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式