专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3951870A1 METHOD FOR FORMING A FAN-OUT PACKAGE STRUCTURE 审中-实审
公开(公告)号：EP3951870A1
公开(公告)日：2022-02-09
申请号：EP21195647.9
申请日：2017-02-10
申请人： MEDIATEK Inc.
发明人： LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen , LIU, Nai-Wei , HUANG, Wei-Che
IPC分类号： H01L25/16 , H01L25/10 , H01L23/498 , H01L23/31 , H01L21/56
摘要： A method for forming a semiconductor package structure, comprises: forming a first RDL structure on a carrier substrate, wherein the first RDL structure ( 110 ) has a first surface and a second surface opposite thereto and the second surface of the first RDL structure ( 110 ) is attached to the carrier substrate; forming a plurality of solder structures (120') on the first surface of the first RDL structure ( 110 ); mounting a first semiconductor die ( 300 ) and a first electronic component ( 400 ) onto the first surface of the first RDL structure ( 110 ), wherein the first semiconductor die ( 300 ) is electrically coupled to the plurality of solder structures through the first RDL structure; forming a first molding compound ( 130 ) on the first surface of the first RDL structure, such that the first semiconductor die ( 300 ) and the plurality of solder structures are embedded in the first molding compound ( 130 ); forming a plurality of openings ( 130 a) in the first molding compound ( 130 ) to correspondingly expose the plurality of solder structures; removing the carrier substrate from the first RDL structure; and mounting a second electronic component ( 500 ) onto the second surface of the first RDL structure after removing the carrier substrate.
Fig. 3 D

2. 发明公开

EP3104409A2 SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体封装组件及其形成方法
公开(公告)号：EP3104409A2
公开(公告)日：2016-12-14
申请号：EP16166593.0
申请日：2016-04-22
申请人： MediaTek, Inc
发明人： LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen
IPC分类号： H01L23/538 , H01L25/16 , H01L25/10 , H01L21/60 , H01L21/56
CPC分类号： H01L25/16 , H01L21/568 , H01L21/78 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/16145 , H01L2224/16265 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73209 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81815 , H01L2224/92124 , H01L2224/92225 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/37001 , H01L2924/014 , H01L2924/00012 , H01L2224/83 , H01L2224/81 , H01L2924/00
摘要： A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die (100). A redistribution layer (RDL) structure (230) is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active (140) or passive element (150) is disposed between the semiconductor die and the RDL structure. A molding compound (220) surrounds the semiconductor die and the active or passive element.
摘要翻译：提供半导体封装组件。该半导体封装组件包括半导体封装。该半导体封装包括半导体管芯（100）。再分布层（RDL）结构（230）设置在半导体管芯上并电连接到半导体管芯。有源（140）或无源元件（150）设置在半导体管芯和RDL结构之间。模塑料（220）围绕半导体管芯和有源或无源元件。

3. 发明公开

EP3091573A2 SEMICONDUCTOR CHIP PACKAGE ASSEMBLY WITH IMPROVED HEAT DISSIPATION PERFORMANCE 审中-公开
标题翻译： HALBLEITER-CHIPPACKUNGSANORDNUNG MIT VERBESSERTERWÄRMEABLEITUNGSLEISTUNG
公开(公告)号：EP3091573A2
公开(公告)日：2016-11-09
申请号：EP16161852.5
申请日：2016-03-23
申请人： MediaTek, Inc
发明人： HSIAO, Ching-Wen , LIN, Tzu-Hung , PENG, I-Hsuan , HSIEH, Tung-Hsien , CHANG, Sheng-Ming
IPC分类号： H01L25/16 , H01L25/10 , H01L23/538 , H01L23/34 , H01L23/50
CPC分类号： H01L23/3675 , H01L23/3114 , H01L23/3121 , H01L23/3677 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L23/50 , H01L23/5389 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/02373 , H01L2224/0401 , H01L2224/04105 , H01L2224/05572 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16055 , H01L2224/16057 , H01L2224/16227 , H01L2224/16265 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/92125 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06589 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/10253 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/00012 , H01L2924/014 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor chip package assembly (1) includes a package substrate (200) having a chip mounting surface (200a); a plurality of solder pads (212) disposed on the chip mounting surface; a first dummy pad (211) and a second dummy pad (211) spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask (202) on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package (100) mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls (250) on respective said solder pads (212); a discrete device (150)having a first terminal (151) and a second terminal (152) disposed between the chip package and the package substrate; a first solder (154) connecting the first terminal with the first dummy pad (211) and the chip package (100); and a second solder (154) connecting the second terminal (152) with the second dummy pad (211) and the chip package (100).
摘要翻译：半导体芯片封装组件（1）包括具有芯片安装表面（200a）的封装衬底（200）; 设置在所述芯片安装表面上的多个焊盘（212）; 与设置在芯片安装表面上的第一虚拟焊盘间隔开的第一虚拟焊盘（211）和第二虚拟焊盘（211）; 在芯片安装表面上的焊接掩模（202），并且部分地覆盖焊盘，第一虚拟焊盘和第二虚拟焊盘; 芯片封装（100），其安装在所述芯片安装表面上并且通过在所述焊盘（212）上的多个焊球（250）电连接到所述封装基板; 具有设置在所述芯片封装和所述封装基板之间的第一端子（151）和第二端子（152）的分立器件（150）将第一端子与第一虚拟焊盘（211）和芯片封装（100）连接的第一焊料（154）; 以及将第二端子（152）与第二虚拟焊盘（211）和芯片封装（100）连接的第二焊料（154）。

4. 发明公开

EP4362375A1 CENTER RU996 TONE PLAN DESIGNS FOR WIDE BANDWIDTH 240MHZ IN WIRELESS COMMUNICATIONS 审中-公开
公开(公告)号：EP4362375A1
公开(公告)日：2024-05-01
申请号：EP23202998.3
申请日：2023-10-11
申请人： MediaTek Inc.
发明人： HU, Shengquan , HSIAO, Ching-Wen , LIU, Jianhan , PARE, Jr., Thomas Edward
IPC分类号： H04L5/00 , H04W52/00 , H04W72/00
CPC分类号： H04L5/001 , H04W52/00 , H04L5/0037
摘要： Various schemes pertaining to center 996-tone resource unit, RU996, tone plan designs for wide bandwidth 240MHz in wireless communications are described. A communication entity generates at least one 996-tone resource unit, RU996. The communication entity then communicates wirelessly using the at least one RU996 in a 240MHz bandwidth. The at least one RU996 includes a center RU996 that is centered around five or more direct-current, DC, tones.

5. 发明授权

EP3125292B1 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
公开(公告)号：EP3125292B1
公开(公告)日：2020-03-25
申请号：EP16175908.9
申请日：2016-06-23
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , HSIAO, Ching-Wen , PENG, I-Hsuan
IPC分类号： H01L23/538 , H01L25/065

6. 发明公开

EP3208848A3 FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：扇出包装结构及其形成方法
公开(公告)号：EP3208848A3
公开(公告)日：2017-10-04
申请号：EP17155522.0
申请日：2017-02-10
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen , LIU, Nai-Wei , HUANG, Wei-Che
IPC分类号： H01L25/16 , H01L25/10 , H01L23/498 , H01L23/31 , H01L21/56
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2224/0401 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/81005 , H01L2225/0651 , H01L2225/06568 , H01L2225/06582 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/37001 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor package structure including a first semiconductor package (10') is provided. The first semiconductor package includes a first redistribution layer (RDL) (110) structure having a first surface (110a) and a second surface (110b) opposite thereto. A first semiconductor die (300) is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound (130) is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder structures (120') is embedded in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure and the first molding compound comprises a plurality of openings (130a) to correspondingly expose the plurality of solder structures.. A method for forming the semiconductor package is also provided.
摘要翻译：提供了包括第一半导体封装（10'）的半导体封装结构。第一半导体封装包括具有第一表面（110a）和与其相对的第二表面（110b）的第一再分布层（RDL）（110）结构。第一半导体管芯（300）设置在第一RDL结构的第一表面上并且与第一RDL结构的第一表面电耦合。第一模塑料（130）设置在第一RDL结构的第一表面上并围绕第一半导体管芯。多个焊料结构（120'）嵌入第一模塑料中并且通过第一RDL结构电耦合到第一半导体管芯，并且第一模塑料包括多个开口（130a）以相应地暴露多个焊料结构还提供了一种用于形成半导体封装的方法。

7. 发明公开

EP3208848A2 FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
公开(公告)号：EP3208848A2
公开(公告)日：2017-08-23
申请号：EP17155522.0
申请日：2017-02-10
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen , LIU, Nai-Wei , HUANG, Wei-Che
IPC分类号： H01L25/16 , H01L25/10 , H01L23/498 , H01L23/31 , H01L21/56
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2224/0401 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/81005 , H01L2225/0651 , H01L2225/06568 , H01L2225/06582 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/37001 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor package structure including a first semiconductor package (10') is provided. The first semiconductor package includes a first redistribution layer (RDL) (110) structure having a first surface (110a) and a second surface (110b) opposite thereto. A first semiconductor die (300) is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound (130) is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder structures (120') is embedded in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure and the first molding compound comprises a plurality of openings (130a) to correspondingly expose the plurality of solder structures.. A method for forming the semiconductor package is also provided.

8. 发明公开

EP3133644A1 BALL GRID ARRAY PACKAGES INCLUDING A HEXAGONAL BALL ARRAY 审中-公开
标题翻译： KGGELGITTERANORDNUNG（球形阵列）-GEHÄUSENAUFWEISEND HEXAGONALE KUGELANORDNUNG
公开(公告)号：EP3133644A1
公开(公告)日：2017-02-22
申请号：EP16176438.6
申请日：2016-06-27
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , HSIAO, Ching-Wen , PENG, I-Hsuan , LIU, Nai-Wei
IPC分类号： H01L23/498 , H01L23/485
CPC分类号： H01L24/14 , H01L23/3107 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L24/19 , H01L24/20 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/13014 , H01L2224/13016 , H01L2224/13024 , H01L2224/131 , H01L2224/14131 , H01L2224/14133 , H01L2224/14134 , H01L2224/14153 , H01L2224/14177 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/14 , H01L2924/1436 , H01L2924/15311 , H01L2924/15313 , H01L2924/18162 , H01L2924/19102 , H01L2924/381 , H01L2924/014 , H01L2924/00012
摘要： A ball grid array (BGA) (100a) for an integrated circuit package (1) includes an array of connection points (502) derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package (1), increasing the density of the connection points (502) and providing higher escape routing. According to one embodiment, the connection points (502) are solder balls (50) mounted on a lower surface of the integrated circuit package (1). The ball grid array (100a) may contain the hexagonal array in a second region (102) and an array of connection points (501) arranged in a square grid-shaped or a rectangular pattern in a first region (101), wherein the connection point pitches in the first and second regions (101, 102) may be the same or different. The teaching is applicable to all types of packages which include a BGA, including a chip scale package (CSP) BGA, a ceramic BGA (CBGA), a land grid array (LGA) package, fan-out packages or package-on-package (PoP).
摘要翻译：用于集成电路封装（1）的球栅阵列（BGA）（100a）包括从集成电路封装（1）的至少一个或多个部分中重复的六边形图案的基本单元导出的连接点阵列（502）），增加连接点（502）的密度并提供较高的逃生路线。根据一个实施例，连接点（502）是安装在集成电路封装（1）的下表面上的焊球（50）。球栅阵列（100a）可以包含位于第一区域（101）中的第二区域（102）中的六边形阵列和布置成方格栅格或矩形图案的连接点阵列（501），其中连接第一和第二区域（101,102）中的点间距可以相同或不同。该教学适用于包括BGA的所有类型的封装，包括芯片级封装（CSP）BGA，陶瓷BGA（CBGA），栅格阵列（LGA）封装，扇出封装或封装封装（POP）。

9. 发明公开

EP3096350A1 SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体封装组件及其形成方法
公开(公告)号：EP3096350A1
公开(公告)日：2016-11-23
申请号：EP16166762.1
申请日：2016-04-24
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , HSIAO, Ching-Wen , PENG, I-Hsuan
IPC分类号： H01L21/60 , H01L23/485 , H01L25/10 , H01L23/538 , H01L23/31
CPC分类号： H01L25/16 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76879 , H01L21/78 , H01L23/3114 , H01L23/49811 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/5385 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/73 , H01L24/80 , H01L24/89 , H01L24/92 , H01L24/96 , H01L25/105 , H01L25/50 , H01L2224/02317 , H01L2224/02319 , H01L2224/02331 , H01L2224/02371 , H01L2224/02372 , H01L2224/02379 , H01L2224/03002 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/08147 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/73259 , H01L2224/80003 , H01L2224/80006 , H01L2224/802 , H01L2224/8083 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/96 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/18162 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/37001 , H01L2924/00014 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/80001
摘要： A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.
摘要翻译：提供半导体封装组件。该半导体封装组件包括第一半导体封装。第一半导体封装包括第一半导体管芯。第一重新分布层（RDL）结构耦合到第一半导体管芯且包括第一导电迹线。半导体封装组件还包括结合到第一半导体封装的第二半导体封装。第二半导体封装包括第二半导体管芯。第二半导体管芯的有源表面面向第一半导体管芯的有源表面。第二RDL结构耦合到第二半导体管芯且包括第二导电迹线。第一导电迹线与第二导电迹线直接接触。

10. 发明公开

EP3096349A1 SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译： HALBLEITERGEHÄUSEANORDNUNGUND VERFAHREN ZUR FORMUNG DAVON
公开(公告)号：EP3096349A1
公开(公告)日：2016-11-23
申请号：EP16164590.8
申请日：2016-04-10
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , HSIAO, Ching-Wen , PENG, I-Hsuan
IPC分类号： H01L21/60 , H01L23/485 , H01L25/10 , H01L23/538 , H01L23/31
CPC分类号： H01L25/0652 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/3107 , H01L23/49811 , H01L23/5226 , H01L23/528 , H01L23/5385 , H01L23/5389 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68359 , H01L2224/0231 , H01L2224/02319 , H01L2224/02373 , H01L2224/02379 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/221 , H01L2224/32145 , H01L2224/73259 , H01L2224/73267 , H01L2224/81005 , H01L2224/8385 , H01L2224/9202 , H01L2224/96 , H01L2225/06548 , H01L2225/06555 , H01L2225/1035 , H01L2225/1058 , H01L2924/18161 , H01L2924/18162 , H01L2924/37001 , H01L2924/014 , H01L2224/19
摘要： A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die. The first RDL structure is positioned between the first semiconductor die and the second RDL structure.
摘要翻译：提供半导体封装组件。半导体封装组件包括第一半导体封装。第一半导体封装包括第一半导体管芯。第一再分配层（RDL）结构耦合到第一半导体管芯。半导体封装组件还包括结合到第一半导体封装的第二半导体封装。第二半导体封装包括第二半导体管芯。第二半导体管芯的有源表面面向第一半导体管芯的有效表面。第二RDL结构耦合到第二半导体管芯。第一RDL结构位于第一半导体管芯和第二RDL结构之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式