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1. 发明公开

EP3951870A1 METHOD FOR FORMING A FAN-OUT PACKAGE STRUCTURE 审中-实审
公开(公告)号：EP3951870A1
公开(公告)日：2022-02-09
申请号：EP21195647.9
申请日：2017-02-10
申请人： MEDIATEK Inc.
发明人： LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen , LIU, Nai-Wei , HUANG, Wei-Che
IPC分类号： H01L25/16 , H01L25/10 , H01L23/498 , H01L23/31 , H01L21/56
摘要： A method for forming a semiconductor package structure, comprises: forming a first RDL structure on a carrier substrate, wherein the first RDL structure ( 110 ) has a first surface and a second surface opposite thereto and the second surface of the first RDL structure ( 110 ) is attached to the carrier substrate; forming a plurality of solder structures (120') on the first surface of the first RDL structure ( 110 ); mounting a first semiconductor die ( 300 ) and a first electronic component ( 400 ) onto the first surface of the first RDL structure ( 110 ), wherein the first semiconductor die ( 300 ) is electrically coupled to the plurality of solder structures through the first RDL structure; forming a first molding compound ( 130 ) on the first surface of the first RDL structure, such that the first semiconductor die ( 300 ) and the plurality of solder structures are embedded in the first molding compound ( 130 ); forming a plurality of openings ( 130 a) in the first molding compound ( 130 ) to correspondingly expose the plurality of solder structures; removing the carrier substrate from the first RDL structure; and mounting a second electronic component ( 500 ) onto the second surface of the first RDL structure after removing the carrier substrate.
Fig. 3 D

2. 发明公开

EP3104409A2 SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体封装组件及其形成方法
公开(公告)号：EP3104409A2
公开(公告)日：2016-12-14
申请号：EP16166593.0
申请日：2016-04-22
申请人： MediaTek, Inc
发明人： LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen
IPC分类号： H01L23/538 , H01L25/16 , H01L25/10 , H01L21/60 , H01L21/56
CPC分类号： H01L25/16 , H01L21/568 , H01L21/78 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/16145 , H01L2224/16265 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73209 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81815 , H01L2224/92124 , H01L2224/92225 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/37001 , H01L2924/014 , H01L2924/00012 , H01L2224/83 , H01L2224/81 , H01L2924/00
摘要： A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die (100). A redistribution layer (RDL) structure (230) is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active (140) or passive element (150) is disposed between the semiconductor die and the RDL structure. A molding compound (220) surrounds the semiconductor die and the active or passive element.
摘要翻译：提供半导体封装组件。该半导体封装组件包括半导体封装。该半导体封装包括半导体管芯（100）。再分布层（RDL）结构（230）设置在半导体管芯上并电连接到半导体管芯。有源（140）或无源元件（150）设置在半导体管芯和RDL结构之间。模塑料（220）围绕半导体管芯和有源或无源元件。

3. 发明公开

EP3091573A2 SEMICONDUCTOR CHIP PACKAGE ASSEMBLY WITH IMPROVED HEAT DISSIPATION PERFORMANCE 审中-公开
标题翻译： HALBLEITER-CHIPPACKUNGSANORDNUNG MIT VERBESSERTERWÄRMEABLEITUNGSLEISTUNG
公开(公告)号：EP3091573A2
公开(公告)日：2016-11-09
申请号：EP16161852.5
申请日：2016-03-23
申请人： MediaTek, Inc
发明人： HSIAO, Ching-Wen , LIN, Tzu-Hung , PENG, I-Hsuan , HSIEH, Tung-Hsien , CHANG, Sheng-Ming
IPC分类号： H01L25/16 , H01L25/10 , H01L23/538 , H01L23/34 , H01L23/50
CPC分类号： H01L23/3675 , H01L23/3114 , H01L23/3121 , H01L23/3677 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L23/50 , H01L23/5389 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/02373 , H01L2224/0401 , H01L2224/04105 , H01L2224/05572 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16055 , H01L2224/16057 , H01L2224/16227 , H01L2224/16265 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/92125 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06589 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/10253 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/00012 , H01L2924/014 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor chip package assembly (1) includes a package substrate (200) having a chip mounting surface (200a); a plurality of solder pads (212) disposed on the chip mounting surface; a first dummy pad (211) and a second dummy pad (211) spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask (202) on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package (100) mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls (250) on respective said solder pads (212); a discrete device (150)having a first terminal (151) and a second terminal (152) disposed between the chip package and the package substrate; a first solder (154) connecting the first terminal with the first dummy pad (211) and the chip package (100); and a second solder (154) connecting the second terminal (152) with the second dummy pad (211) and the chip package (100).
摘要翻译：半导体芯片封装组件（1）包括具有芯片安装表面（200a）的封装衬底（200）; 设置在所述芯片安装表面上的多个焊盘（212）; 与设置在芯片安装表面上的第一虚拟焊盘间隔开的第一虚拟焊盘（211）和第二虚拟焊盘（211）; 在芯片安装表面上的焊接掩模（202），并且部分地覆盖焊盘，第一虚拟焊盘和第二虚拟焊盘; 芯片封装（100），其安装在所述芯片安装表面上并且通过在所述焊盘（212）上的多个焊球（250）电连接到所述封装基板; 具有设置在所述芯片封装和所述封装基板之间的第一端子（151）和第二端子（152）的分立器件（150）将第一端子与第一虚拟焊盘（211）和芯片封装（100）连接的第一焊料（154）; 以及将第二端子（152）与第二虚拟焊盘（211）和芯片封装（100）连接的第二焊料（154）。

4. 发明公开

EP4387181A2 LTF AND STF TRANSMISSION FOR WIDE BANDWIDTH 240MHZ WITH MORE DC TONES IN WIRELESS COMMUNICATIONS 审中-实审
公开(公告)号：EP4387181A2
公开(公告)日：2024-06-19
申请号：EP23211682.2
申请日：2023-11-23
申请人： MediaTek Inc.
发明人： HU, Shengquan , HSIAO, Ching-Wen , LIU, Jianhan , PARE JR., Thomas Edward
IPC分类号： H04L27/26 , H04L5/00
CPC分类号： H04L5/0048 , H04L27/26132 , H04L27/2614
摘要： Various schemes pertaining to long training field and short training field transmission for wide bandwidth 240MHz with more direct-current tones in wireless communications are described. A processor (1312, 1322) of an apparatus (1310, 1320) generates either or both of a long training field and a short training field of a physical-layer protocol data unit with a center 996-tone resource unit having more than a predetermined number of direct-current tones (1410). The processor (1312, 1322) then performs a wireless communication in a wide bandwidth (e.g., 240MHz) with the physical-layer protocol data unit (1420).

5. 发明公开

EP4167653A1 METHOD AND APPARATUS FOR LOW-POWER LISTEN IN WIRELESS COMMUNICATIONS 审中-实审
公开(公告)号：EP4167653A1
公开(公告)日：2023-04-19
申请号：EP22201155.3
申请日：2022-10-12
申请人： MediaTek Inc.
发明人： CHANG, Cheng-Yi , CHOU, Yi-Chun , HSIAO, Ching-Wen , CHEN, Chien-Wei
IPC分类号： H04W52/34
摘要： Techniques pertaining to low-power enhanced multi-link single radio, EMLSR, listen in wireless communications are described. A first multi-link device, MLD, reduces power consumption while supporting a latency-sensitive application by performing certain operations. The first MLD first listens at a lower power in a narrower bandwidth to receive an initial physical-layer protocol data unit, PPDU, from a second MLD as part of a frame exchange (612). In response to receiving the initial PPDU, the first MLD switches from the narrower bandwidth to a wider bandwidth to complete the frame exchange with the second MLD in the wider bandwidth (614). In reducing the power consumption, the first MLD reduces its power consumption to the lower power when operating in the narrower bandwidth compared to a higher power used by the first MLD when operating in the wider bandwidth.

6. 发明公开

EP4167631A1 COVERAGE ENHANCEMENT FOR 6GHZ LONG RANGE WIRELESS COMMUNICATIONS 审中-实审
公开(公告)号：EP4167631A1
公开(公告)日：2023-04-19
申请号：EP22201406.0
申请日：2022-10-13
申请人： MediaTek Inc.
发明人： CHANG, Cheng-Yi , HSIAO, Ching-Wen , SHIU, Shu-Ping
IPC分类号： H04W28/06 , H04W84/12
摘要： Techniques pertaining to coverage enhancement for 6GHz wireless communications are described. A first station, STA, communicates with a second STA in a 6GHz wireless band and/or low-power indoor, LPI, channels (810). The first STA performs a receiving signal combination and detection across multiple bandwidths such that a power level or a signal strength is enhanced in communicating with the second STA (820).

7. 发明授权

EP3076429B1 SEMICONDUCTOR PACKAGE ASSEMBLY WITH EMBEDDED MULTI-LAYER CERAMIC CAPACITOR OR CHIP-CAP CAPACITOR 有权
公开(公告)号：EP3076429B1
公开(公告)日：2020-05-06
申请号：EP16160070.5
申请日：2016-03-14
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen
IPC分类号： H01L23/538 , H01L25/16 , H01L25/10 , H01L23/498

8. 发明公开

EP3154078A3 FAN-OUT WAFER LEVEL PACKAGE STRUCTURE 无效
标题翻译：扇出晶圆级封装结构
公开(公告)号：EP3154078A3
公开(公告)日：2017-05-31
申请号：EP16184667.0
申请日：2016-08-18
申请人： MediaTek Inc.
发明人： LIU, Nai-Wei , LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen , HUANG, Wei-Che
IPC分类号： H01L21/56 , H01L21/60
CPC分类号： H01L23/544 , H01L21/561 , H01L21/568 , H01L23/562 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/29016 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/9222 , H01L2225/1035 , H01L2225/1041 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/3511 , H01L2924/3512 , H01L2924/35121 , H01L2924/37001
摘要： A semiconductor package structure is provided. The structure includes a molding compound (100) having a dicing lane region (L). A semiconductor die (200) is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface (200a) and a second surface (200b) opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure (102) disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photosensitive material (102a) and has an opening (103) aligned with the dicing lane region.
摘要翻译：提供了一种半导体封装结构。该结构包括具有切割道区域（L）的模塑料（100）。半导体管芯（200）设置在模塑料中并被切割线区域包围。半导体管芯具有第一表面（200a）和与其相对的第二表面（200b），并且第一和第二表面从模塑料露出。该结构还包括布置在半导体管芯的第一表面上并覆盖模塑料的再分布层（RDL）结构（102）。 RDL结构包括光敏材料（102a）并具有与切割道区域对齐的开口（103）。

9. 发明公开

EP3154078A2 FAN-OUT WAFER LEVEL PACKAGE STRUCTURE 无效
标题翻译：输出风扇房屋结构在晶片级
公开(公告)号：EP3154078A2
公开(公告)日：2017-04-12
申请号：EP16184667.0
申请日：2016-08-18
申请人： MediaTek Inc.
发明人： LIU, Nai-Wei , LIN, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen , HUANG, Wei-Che
IPC分类号： H01L21/56
CPC分类号： H01L23/544 , H01L21/561 , H01L21/568 , H01L23/562 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/29016 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/9222 , H01L2225/1035 , H01L2225/1041 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/3511 , H01L2924/3512 , H01L2924/35121 , H01L2924/37001
摘要： A semiconductor package structure is provided. The structure includes a molding compound (100) having a dicing lane region (L). A semiconductor die (200) is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface (200a) and a second surface (200b) opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure (102) disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photosensitive material (102a) and has an opening (103) aligned with the dicing lane region.

10. 发明公开

EP3073525A2 SEMICONDUCTOR PACKAGE ASSEMBLY WITH A METAL-INSULATOR-METAL CAPACITOR STRUCTURE 有权
标题翻译：具有金属 - 绝缘体 - 金属电容器结构的半导体封装组件
公开(公告)号：EP3073525A2
公开(公告)日：2016-09-28
申请号：EP16159135.9
申请日：2016-03-08
申请人： MediaTek, Inc
发明人： Lin, Tzu-Hung , PENG, I-Hsuan , HSIAO, Ching-Wen
IPC分类号： H01L23/522 , H01L23/538 , H01L25/16 , H01L25/10 , H01L25/065
摘要： The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die (302). A first redistribution layer (RDL) structure (308) is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace (452b) disposed at a first layer-level. A second conductive trace (454b) is disposed at a second layer-level. A first inter-metal dielectric (IMD) layerc (318) and a second intermetal dielectric (IMD) layer (456b), which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace, resulting in a metal-insulator-metal (MIM) capacitor structure.
摘要翻译：本发明提供了一种半导体封装组件。该半导体封装组件包括包含第一半导体管芯（302）的第一半导体封装。第一重新分布层（RDL）结构（308）耦合到第一半导体管芯。第一再分布层（RDL）结构包括布置在第一层级的第一导电迹线（452b）。第二导电迹线（454b）设置在第二层级。在第一金属间电介质（IMD）层旁边的第一金属间电介质（IMD）层c（318）和第二金属间电介质（IMD）层（456b）设置在第一导电迹线与第二导电迹线导电迹线，导致金属 - 绝缘体 - 金属（MIM）电容器结构。

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