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1. 发明专利

GB2437465A Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device, and electronic device using multilayer wiring board 未知
公开(公告)号：GB2437465A
公开(公告)日：2007-10-24
申请号：GB0714966
申请日：2006-02-01
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI , ASAHI TOSHIYUKI , MIKI KATSUMASA , KATSUMATA MASAAKI , SAITOU YOSHIYUKI , NAKAYAMA TAKESHI
IPC分类号： H05K1/18 , H01L23/31 , H01L23/498
摘要： A multilayer wiring board is provided with a plurality of wiring boards which include a plurality of wiring layers including a pounding layer and a power supply layer a solid electrolytic capacitor wherein an insulating oxide film layer, an electrolyte layer and a conductive layer are successively formed on one plane or both planes of a foil-like metal base body; and a conductive member penetrating in a thickness direction of the wiring boards. The solid electrolytic capacitor is arranged to be sandwiched between the wiring boards, the conductive layer is connected to a grounding electrode formed on the grounding layer, and the foil-like metal base body is connected to a power supply electrode formed on the power supply layer.

2. 发明专利

GB2437465B Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device, and electronic device using multilayer wiring board 未知
公开(公告)号：GB2437465B
公开(公告)日：2010-11-17
申请号：GB0714966
申请日：2006-02-01
申请人： MATSUSHITA ELECTRIC IND CO LTD , PANASONIC CORP
发明人： SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI , ASAHI TOSHIYUKI , MIKI KATSUMASA , KATSUMATA MASAAKI , SAITOU YOSHIYUKI , NAKAYAMA TAKESHI
IPC分类号： H05K1/18 , H01L23/31 , H01L23/498
摘要： A multilayered substrate includes a plurality of circuit boards including a plurality of wiring layers including a grounding layer and a power layer, a solid electrolytic capacitor having an insulative oxide film layer, an electrolytic layer, and a conductor layer sequentially formed on one surface or both surfaces of a foil-like metal substrate, and a conductive substance passing through the circuit board across a thickness thereof. The solid electrolytic capacitor is disposed to be held between the plurality of circuit boards. The conductor layer is connected to a grounding electrode formed on the grounding layer, the foil-like metal substrate being connected to a power electrode formed on the power layer.

3. 发明专利

JP2008130722A Circuit board with built-in solid-state electrolytic capacitor, and its manufacturing method 审中-公开
标题翻译：具有内置固态电解电容器的电路板及其制造方法
公开(公告)号：JP2008130722A
公开(公告)日：2008-06-05
申请号：JP2006312597
申请日：2006-11-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMAMOTO YOSHIYUKI , SUGAYA YASUHIRO
IPC分类号： H01G9/012 , H01G9/00 , H01G9/004 , H01G9/04
摘要： PROBLEM TO BE SOLVED: To electrically connect an aluminum metal layer to a through-hole copper plating layer not through an oxide layer on the surface of the aluminum, and to obtain low-resistance connection between the aluminum metal layer of an anode and the through-hole of a solid-state electrolytic capacitor.
SOLUTION: This circuit board with the built-in solid-state electrolytic capacitor comprises a first plating layer 9 and a second plating layer 10 formed in the through-hole, the metal plating layer using an alkaline plating solution formed on the surface of the anode 1 on the wall surface in the through-hole 8 as the first plating layer 9, and the metal plating layer formed on the surface of an insulating resin layer 3 on the wall surface in the through-hole 8 and on the entire wall surface in the through-hole 8 including the surface of the first plating layer 9 as the second plating layer 10.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了将铝金属层与通孔铜镀层不是通过铝表面上的氧化物层电连接，并且在阳极的铝金属层之间获得低电阻连接和固态电解电容器的通孔。
解决方案：具有内置固态电解电容器的电路板包括形成在通孔中的第一镀层9和第二镀层10，金属镀层使用形成在表面上的碱性电镀液作为第一镀层9的通孔8的壁面上的阳极1和在通孔8的壁面上形成在绝缘树脂层3的表面上的金属镀层，整个包括第一镀层9作为第二镀层10的表面的通孔8中的壁表面。（C）2008，JPO＆INPIT

4. 发明专利

JP2007251101A Circuit substrate with built-in solid electrolytic capacitor, interposer using it and package 审中-公开
标题翻译：具有内置固体电解电容器的电路基板，使用它和包装的插接器
公开(公告)号：JP2007251101A
公开(公告)日：2007-09-27
申请号：JP2006076320
申请日：2006-03-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMAMOTO YOSHIYUKI , TAKASE YOSHIHISA , SUGAYA YASUHIRO
IPC分类号： H05K1/18 , H01G2/06 , H01G9/08 , H01L23/12 , H01L23/32 , H05K1/11
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a substrate with a built-in solid electrolytic capacitor which can achieve low resistance connection between an aluminum metallic layer which is an anode of the solid electrolytic capacitor and a through-hole. SOLUTION: In the substrate with a built-in solid electrolytic capacitor, a sheet-like solid electrolytic capacitor consisting of an anode 1 of an aluminum metallic layer and a cathode 6 of a silver paste layer is built in an insulating resin 3. A front layer and a back layer are formed of a metallic layer 4. The anode 1 is connected to the metallic layer 4 of the front layer and the back layer via a through-hole 8. The cathode 6 is connected to the metallic layer 4 of the front layer by means of a conductor paste. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种内置固体电解电容器的基板，其可以实现作为固体电解电容器的阳极的铝金属层与通孔之间的低电阻连接。解决方案：在具有内置固体电解电容器的基板中，将由铝金属层的阳极1和银膏层的阴极6组成的片状固体电解电容器构建在绝缘树脂3中由金属层4形成前层和背层。阳极1经由通孔8与前层的金属层4和背层连接。阴极6与金属层 4的前层通过导体糊。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006173441A Method for manufacturing solid electrolytic capacitor 审中-公开
标题翻译：制造固体电解电容器的方法
公开(公告)号：JP2006173441A
公开(公告)日：2006-06-29
申请号：JP2004365691
申请日：2004-12-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIKI KATSUMASA , YAMAMOTO YOSHIYUKI , SUGAYA YASUHIRO , KATSUMATA MASAAKI
IPC分类号： H01G9/00 , H01G9/012 , H01G9/052
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a solid electrolytic capacitor that not only suppresses bend and deformation in the manufacturing process, but also facilitates transportation to ensure productivity improvement and enables the capacitor to be easily implemented as a device.
SOLUTION: After pasting a valve metal sheet 1 to a base material 2, the valve metal sheet 1 is divided to form two solid electrolytic layers 7A and 7B and a collector layer 8 by the polymerization method, so that the thin solid electrolytic capacitor and solid electrolytic capacitor device array can be manufactured easily.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种制造固体电解电容器的方法，其不仅抑制制造工艺中的弯曲和变形，而且便于运输以确保生产率的提高，并且能够容易地实现电容器作为装置。解决方案：在将阀金属片1粘贴到基材2之后，通过聚合方法将阀金属片1分割成两个固体电解质层7A和7B以及集电层8，使得固体电解质电容器和固体电解电容器阵列可以容易地制造。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2004311788A Sheet module and its manufacturing method 审中-公开
标题翻译：表格模块及其制造方法
公开(公告)号：JP2004311788A
公开(公告)日：2004-11-04
申请号：JP2003104553
申请日：2003-04-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMAMOTO YOSHIYUKI , NAKATANI SEIICHI , KOJIMA TOSHIYUKI
IPC分类号： H01L23/28 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/29 , H01L23/31
CPC分类号： H01L2221/68354 , H01L2224/16 , H01L2924/01019 , H01L2924/01078
摘要： PROBLEM TO BE SOLVED: To provide a high density semiconductor built-in module having a felexible performance with an identical material used for an underfill and an insulating layer of the semiconductor, and to provide a method for manufacturing it. SOLUTION: The semiconductor built-in module has an electrically insulating layer (101) comprising a mixture of an inorganic filler and a resin, an interconnection carrier layer having at least an interonnection pattern (102) on one side of the layer (101), an interconnection pattern layer (103) on the other side, an inner via hole (104) for mutually connecting between the pattern (102) and the pattern (103), and a semiconductor (105) embedded in the electrically insulating layer, The external electrode of the semiconductor (105) is connected to the pattern (102) through a projecting electrode (106), an electrically insulating material existing between the external electrode surface of the semiconductor (105) and the interconnection carrier comprises the same material as the electrically insulating layer, and the pattern layer (103) on the layer (101) and the other side of the layer (101) forms approximately identical surface. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有与用于底部填充物和半导体的绝缘层的相同材料具有柔性性能的高密度半导体内置模块，并提供其制造方法。解决方案：半导体内置模块具有包含无机填料和树脂的混合物的电绝缘层（101），在层的一侧至少具有连接图案（102）的互连载体层（ 101），另一侧的互连图案层（103），用于在图案（102）和图案（103）之间相互连接的内部通孔（104）和嵌入电绝缘层中的半导体（105）半导体（105）的外部电极通过突出电极（106）连接到图案（102），存在于半导体（105）的外部电极表面和互连载体之间的电绝缘材料包括相同的材料作为电绝缘层，层（101）上的图案层（103）和层（101）的另一侧形成大致相同的表面。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2004022610A Interposer, semiconductor package, interposer-manufacturing method, and semiconductor package manufacturing method 审中-公开
公开(公告)号：JP2004022610A
公开(公告)日：2004-01-22
申请号：JP2002171973
申请日：2002-06-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ASAHI TOSHIYUKI , TAGUCHI YUTAKA , SUGAYA YASUHIRO , KOMATSU SHINGO , YAMAMOTO YOSHIYUKI , KAWAMOTO EIJI
IPC分类号： H01L23/12
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an interposer and a semiconductor package which effectively serve the purpose of turning package density higher, and to provide methods for manufacturing them. SOLUTION: The interposer, which is to be mounted on a packaging substrate, has: an electrical insulator; a substrate-packaging pattern formed on a first surface, which faces the packaging substrate of the electrical insulator for mounting the electrical insulator on the packaging substrate; a semiconductor-packaging pattern formed on a second surface, which doe not face the packaging substrate of the electrical insulator for mounting the semiconductor on the electrical insulator; and a connecting conductor, formed on the electrical insulator for electrically connecting the substrate-packaging pattern and the semiconductor packaging pattern. The interposer is characterized in that it has electronic components formed within the electrical insulator and electrically connected at least to one of the two patterns, which are the substrate-packaging pattern and the semiconductor-packaging pattern. COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2003289128A Circuit component built-in module and method for manufacturing the same 有权
标题翻译：电路组件内置模块及其制造方法
公开(公告)号：JP2003289128A
公开(公告)日：2003-10-10
申请号：JP2003010170
申请日：2003-01-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SUGAYA YASUHIRO , ASAHI TOSHIYUKI , KOMATSU SHINGO , YAMAMOTO YOSHIYUKI , NAKATANI SEIICHI , YUHAKU SEI , OTANI KAZUO , IDOKAWA YOSHINOBU , NISHIYAMA TOSAKU
IPC分类号： H01L25/18 , H01L25/04 , H01L25/10 , H01L25/11
CPC分类号： H01L2224/16 , H01L2224/2402 , H01L2224/73204 , H01L2224/83101 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： PROBLEM TO BE SOLVED: To provide a circuit component built-in module, mounted at high density to be suitably used for various electronic information apparatuses miniaturized with high performance, and to provide a method for manufacturing the component built-in module. SOLUTION: This circuit component built-in module (212) includes electrical insulating substrates (201, 201a), constituted of a mixture containing inorganic filler and heat-hardening resin, a plurality of wiring patterns (202a, 202b, and 202c) formed on at least the main surface of the electrical insulating substrate (201a), a semiconductor chip (203) built-in the electrical insulating substrates (201, 201a), and electrically connected to the wiring pattern (202c), and an inner via (204a) formed passing through the electrical insulating substrate (201a) so that the plurality of wiring patterns (202a, 202b) can be electrically connected. The thickness of the semiconductor chip (203) is set so as to be 30 μm or larger and 100 μm or smaller, and a non-wiring face becomes a grinding face, and the thickness of the circuit component built-in module (212) is set so as to be 80 μm or larger and 200 μm or smaller. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种高密度安装的电路部件内置模块，适合用于高性能小型化的各种电子信息装置，并提供一种制造组件内置模块的方法。解决方案：该电路部件内置模块（212）包括由包含无机填料和加热硬化树脂的混合物构成的电绝缘基板（201,201a），多个布线图案（202a，202b和202c）），至少形成在所述电绝缘基板（201a）的主表面上，内置有所述电绝缘基板（201,201a）的电连接到所述布线图案（202c）的半导体芯片（203）通孔（204a）通过电绝缘基板（201a）形成，使得多个布线图案（202a，202b）可以电连接。将半导体芯片（203）的厚度设定为30μm以上且100μm以下，非布线面成为研磨面，电路部件内置模块（212）的厚度，被设定为80μm以上且200μm以下。版权所有（C）2004，JPO

9. 发明专利

JPH03152763A FM SIGNAL REPRODUCING DEVICE 失效
公开(公告)号：JPH03152763A
公开(公告)日：1991-06-28
申请号：JP29005389
申请日：1989-11-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAMOTO YOSHIYUKI
IPC分类号： H04N5/922 , G11B20/06 , H04N5/92
摘要： PURPOSE:To reduce a power voltage and to save power consumption by providing a level detection circuit detecting a peak output of an equalizer to control a gain of a gain control circuit, an FM demodulation circuit and a dropout detection circuit detecting a dropout of a reproduced FM signal. CONSTITUTION:A gain control circuit 3 controls a gain of a reproduced FM signal and an equalizer 4 changes a frequency characteristic of an output signal level with a control signal applied from other device. A level detection circuit 5 detects its peak output to control a gain of the gain control circuit 3 and a dropout detection circuit 7 detects a dropout of a reproduced FM signal of an FM demodulation circuit 6 connecting to an output terminal of the equalizer 4. Thus, the FM signal subject to gain control is applied to the equalizer 4 and the output is given to the dropout detection circuit 7 so as to apply gain control thereby receiving a desired level, and the change in the FM signal level applied to the equalizer 4 is controlled by the same fluctuation quantity of the gain caused by the equalizer 4. Thus, a low power supply voltage is used and the power consumption is saved.

10. 发明专利

JPH02194794A CHROMINANCE SIGNAL REGENERATING DEVICE 失效
公开(公告)号：JPH02194794A
公开(公告)日：1990-08-01
申请号：JP1380489
申请日：1989-01-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAMOTO NAOKI , UCHIYAMA SHINICHI , YAMAMOTO YOSHIYUKI , USUKI NAOJI
IPC分类号： H04N9/83
摘要： PURPOSE:To obtain a chrominance signal regenerating device with the less deterioration of picture quality and free from the occurrence of color bleeding by using a comb line filter to process the signals of two lines as the comb line filter in an APC loop, and on the other hand, using the comb line filter to process the signals of three lines for a regenerated carrier chrominance signal. CONSTITUTION:In the APC(automatic phase control) loop, a first comb line filter 908 processes the signals of two lines, and a selection circuit 11 selects the output signal of a burst de-emphasis circuit 8 at the time of the regeneration of a standard mode, and selects the output signal of the first comb line filter 908 at the time of the regeneration of a long time mode, and supplies them to a burst gate 12. Then, the phase control of regenerative frequency conversion is performed according to the result of phase comparison between a burst signal extracted from said signal and a reference signal. On the other hand, the signal supplied to a second comb line filter 909 is processed by the arithmetic processing of three lines, and is outputted as the regenerated carrier chrominance signal from an output terminal 10. Thus, the chrominance signal regenerating device with the less deterioration of the picture quality and free from the occurrence of the color bleeding can be obtained.

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