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1. 发明专利

GB2437465A Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device, and electronic device using multilayer wiring board 未知
公开(公告)号：GB2437465A
公开(公告)日：2007-10-24
申请号：GB0714966
申请日：2006-02-01
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI , ASAHI TOSHIYUKI , MIKI KATSUMASA , KATSUMATA MASAAKI , SAITOU YOSHIYUKI , NAKAYAMA TAKESHI
IPC分类号： H05K1/18 , H01L23/31 , H01L23/498
摘要： A multilayer wiring board is provided with a plurality of wiring boards which include a plurality of wiring layers including a pounding layer and a power supply layer a solid electrolytic capacitor wherein an insulating oxide film layer, an electrolyte layer and a conductive layer are successively formed on one plane or both planes of a foil-like metal base body; and a conductive member penetrating in a thickness direction of the wiring boards. The solid electrolytic capacitor is arranged to be sandwiched between the wiring boards, the conductive layer is connected to a grounding electrode formed on the grounding layer, and the foil-like metal base body is connected to a power supply electrode formed on the power supply layer.

2. 发明专利

GB2437465B Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device, and electronic device using multilayer wiring board 未知
公开(公告)号：GB2437465B
公开(公告)日：2010-11-17
申请号：GB0714966
申请日：2006-02-01
申请人： MATSUSHITA ELECTRIC IND CO LTD , PANASONIC CORP
发明人： SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI , ASAHI TOSHIYUKI , MIKI KATSUMASA , KATSUMATA MASAAKI , SAITOU YOSHIYUKI , NAKAYAMA TAKESHI
IPC分类号： H05K1/18 , H01L23/31 , H01L23/498
摘要： A multilayered substrate includes a plurality of circuit boards including a plurality of wiring layers including a grounding layer and a power layer, a solid electrolytic capacitor having an insulative oxide film layer, an electrolytic layer, and a conductor layer sequentially formed on one surface or both surfaces of a foil-like metal substrate, and a conductive substance passing through the circuit board across a thickness thereof. The solid electrolytic capacitor is disposed to be held between the plurality of circuit boards. The conductor layer is connected to a grounding electrode formed on the grounding layer, the foil-like metal substrate being connected to a power electrode formed on the power layer.

3. 发明专利

JP2007285952A Signal analysis device and signal analysis method 审中-公开
标题翻译：信号分析装置及信号分析方法
公开(公告)号：JP2007285952A
公开(公告)日：2007-11-01
申请号：JP2006115177
申请日：2006-04-19
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAYAMA TAKESHI , TAKAHASHI EIJI , IWAKI HIDEKI
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide a signal analysis device for obtaining a more accurate simulation result of the measuring signal of a substrate, and to provide a signal analysis method.
SOLUTION: The signal analysis device comprises a signal difference calculation part 104 for calculating a difference between a signal measurement result and a signal analysis result; a signal analysis result correction part 105 for correcting to add the signal difference to an analysis result of a desired analysis point; an analysis extraction part 106; and a circuit analysis part 107. The signal analysis device enhances a product development efficiency, by adding the difference between the analysis result and the measurement result to the analysis result of the desired analysis point to correct the signal and accurately performing signal monitoring, in a development stage of a product, since the accuracy of the analysis result approximates signal waveform that is being generated on the actual product.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种信号分析装置，用于获得基板的测量信号的更准确的模拟结果，并提供信号分析方法。信号分析装置包括用于计算信号测量结果和信号分析结果之间的差的信号差分计算部分104; 信号分析结果校正部分105，用于校正以将信号差加到期望分析点的分析结果; 分析提取部106; 电路分析部107.信号分析装置通过将分析结果与测量结果之间的差异与所需分析点的分析结果相加来增强产品开发效率，以校正信号并准确地执行信号监视产品的开发阶段，因为分析结果的准确性近似于在实际产品上产生的信号波形。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007285852A Signal measuring method, device, and electronic component 审中-公开
标题翻译：信号测量方法，器件和电子元件
公开(公告)号：JP2007285852A
公开(公告)日：2007-11-01
申请号：JP2006113144
申请日：2006-04-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KINOSHITA TOMOHIRO , NAKAYAMA TAKESHI , SAITO YOSHIYUKI
IPC分类号： G01R31/28 , G01R15/04 , H01C1/04
摘要： PROBLEM TO BE SOLVED: To reduce a change of a signal waveform, caused when reflection generated at a contact point with a probe is transferred to a circuit to be measured, concerning a signal measuring method of a circuit board or the like.
SOLUTION: A circuit element for impedance matching or the like connected to a signal wire 106 is divided into two or more, and the probe 107 is brought into contact with a connection point, and the divided voltage of a signal is measured, to thereby cause reflection of the signal by the circuit element 101 adjacent to the circuit to be measured to be attenuate. Moreover, correction operation is performed, by using each impedance value of the circuit elements 101, 102 and the measured divided voltage, and the signal of a measuring point is led out.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了减少在与探针的接触点产生的反射被传送到要测量的电路时引起的信号波形的变化，涉及电路板等的信号测量方法。＆lt; P＆gt;解决方案：连接到信号线106的用于阻抗匹配等的电路元件被分成两个或更多个，并且探针107与连接点接触，并且测量信号的分压，从而使与被测量电路相邻的电路元件101的信号反射为衰减。此外，通过使用电路元件101,102的每个阻抗值和测量的分压，执行校正操作，并且测量点的信号被引出。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006040265A Flexible board design supporting device and method and program 审中-公开
标题翻译：灵活的板设计支持设备及方法与程序
公开(公告)号：JP2006040265A
公开(公告)日：2006-02-09
申请号：JP2005175877
申请日：2005-06-16
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAYAMA TAKESHI , TANIMOTO SHINICHI , SAITO YOSHIYUKI
IPC分类号： G06F17/50 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a design supporting device for easily designing a flexible printed board.
SOLUTION: This design supporting device is configured to generate, as a prohibited space, a position assumed to be occupied by components on an opposing printed circuit board when the printed circuit board is bent from a bend position and the components. The design reference check of a bendable flexible printed circuit board can be efficiently performed by checking the presence/absence of interference between the components and prohibited spaces.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种易于设计柔性印刷电路板的设计支持装置。解决方案：该设计支持装置被配置为当印刷电路板从弯曲位置和部件弯曲时，作为禁止空间产生假定被相对印刷电路板上的部件占据的位置。通过检查组件和禁止空间之间是否存在干扰，可以有效地执行可弯曲柔性印刷电路板的设计参考检查。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005234701A Design support system, design support method and program 审中-公开
标题翻译：设计支持系统，设计支持方法和程序
公开(公告)号：JP2005234701A
公开(公告)日：2005-09-02
申请号：JP2004040384
申请日：2004-02-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： IKEDA HIROSHI , NAKAYAMA TAKESHI
IPC分类号： G06F17/50 , H05K3/00
CPC分类号： G06F17/5068
摘要： PROBLEM TO BE SOLVED: To provide a design support system that supports operations of local placement designs of objects on a multilayer wiring board and streamlines an operation of verification of design consistency. SOLUTION: Series of dielectrics on opposite sides of a specific dielectric capable of having built-in parts are designated as a first part and a second part, respectively. A first support part 101 holds design information about the placement of objects mounted on the first part in a local design information storage part 141, manages it in response to commands given by a user via an input part 110 and displays the contents on a display part 120 to thereby support the design of the first part. A second support part 201 similarly supports the design of the second part. The first support part 101 and the second support part 201 hold design information about the placement of boundary objects mounted astride both parts in boundary design information storage parts 142 and 242, respectively, and cooperatively and synchronously display the contents on the display parts 110 and 210, respectively. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种设计支持系统，其支持多层布线板上的对象的本地布局设计的操作，并且简化了设计一致性验证的操作。解决方案：能够具有内置部件的特定电介质的相对侧上的电介质系列分别被指定为第一部分和第二部分。第一支撑部分101将关于安装在第一部分上的物体的放置的设计信息保存在本地设计信息存储部分141中，并且响应于用户经由输入部分110给出的命令进行管理，并将其显示在显示部分上从而支持第一部分的设计。第二支撑部分201类似地支撑第二部分的设计。第一支撑部101和第二支撑部201分别保持跨越两部分跨越边界设计信息存储部142和242的边界对象的位置的设计信息，并且在显示部110和210上协同同步地显示内容，分别。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005079318A Module with built-in connector, circuit board employing the same and composite module 审中-公开
标题翻译：具有内置连接器的模块，使用其的电路板和复合模块
公开(公告)号：JP2005079318A
公开(公告)日：2005-03-24
申请号：JP2003307251
申请日：2003-08-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ITO TETSUO , ASAHI TOSHIYUKI , SUGAYA YASUHIRO , NAKAYAMA TAKESHI , SAITO YOSHIYUKI
IPC分类号： H01L23/12 , H05K1/11 , H05K1/18 , H05K3/46 , H01R12/32
摘要： PROBLEM TO BE SOLVED: To provide a module with a built-in connector with less noise which permits high-density mounting to connect a signal to the outside system, a composite module and a circuit substrate which are employing the module with a built-in connector.
SOLUTION: The module with a built-in connector accommodates an electric insulating layer (101) provided with a wiring pattern (104) and at least an electronic component (103) selected from one or more active components and passive components in the electric insulating layer (101), and is electrically connected to the wiring pattern (104) and accommodates one or more of connectors (102) for connecting to an external electrode electrically. The connector (102) is provided with an external wiring inserting unit (105).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供具有较少噪声的内置连接器的模块，其允许高密度安装以将信号连接到外部系统，复合模块和电路基板，其将模块与内置连接器解决方案：具有内置连接器的模块容纳设置有布线图案（104）的电绝缘层（101）和至少选自一个或多个有源部件中的电子部件（103）和无源元件电绝缘层（101），并且电连接到布线图案（104），并且容纳用于电连接到外部电极的一个或多个连接器（102）。连接器（102）设置有外部布线插入单元（105）。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005071131A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005071131A
公开(公告)日：2005-03-17
申请号：JP2003300999
申请日：2003-08-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ASAHI TOSHIYUKI , SUGAYA YASUHIRO , KOJIMA TOSHIYUKI , SAITO YOSHIYUKI , NAKAYAMA TAKESHI
IPC分类号： G06K19/073
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a physical security function and high information reliability. SOLUTION: This semiconductor device 100 includes an insulation layer 101, a wiring pattern 102 formed at the insulation layer 101, a via hole conductor 103 which connects between the wiring patterns 102 and a semiconductor 104 which is arranged inside the insulation layer 101 and mounted on the wiring pattern 102. Bonding strength between the insulation layer 101 and the semiconductor 104 is higher than the fracture strength of the semiconductor 104. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有物理安全功能和高信息可靠性的半导体器件。解决方案：该半导体器件100包括绝缘层101，形成在绝缘层101处的布线图案102，连接布线图案102的通孔导体103和布置在绝缘层101内部的半导体104 并且安装在布线图案102上。绝缘层101和半导体104之间的结合强度高于半导体104的断裂强度。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004343098A Multilayer circuit board and integrated circuit using it 审中-公开
公开(公告)号：JP2004343098A
公开(公告)日：2004-12-02
申请号：JP2004125933
申请日：2004-04-21
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAGI HIROYOSHI , NAKATANI SEIICHI , SAITO YOSHIYUKI , NAKAYAMA TAKESHI
IPC分类号： H05K9/00 , H05K3/46 , H05K7/20
摘要： PROBLEM TO BE SOLVED: To easily prevent the occurrence of noise due to causes such as reflection and ringing while preventing increase in the ground occupancy rate in a multilayer circuit board.
SOLUTION: A multilayer circuit board 101 is equipped with, for example, alternating layers of electrical insulating layers 103 and wiring layers 114, conductors 115 which electrically connect the wiring layers and penetrate one electrical insulating layer in the thickness direction of the electrical insulating layer, and plating layers 107 which are formed so as to cover the sides of the electrical insulating layers and are electrically connected to a ground wiring 106. The impedance of a signal transmission conductor 102a positioned at an end portion of one electrical insulating layer 103 is controlled by a grounding conductor 105a positioned so that the signal transmission conductor 102a is placed between one plating layer 107 and the grounding conductor 105a and by the plating layers 107.
COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP2002299842A MULTILAYER SUBSTRATE, METHOD AND DEVICE FOR DESIGNING MULTILAYER SUBSTRATE, PROGRAM AND COMPUTER READABLE MEMORY MEDIUM 审中-公开
公开(公告)号：JP2002299842A
公开(公告)日：2002-10-11
申请号：JP2001395053
申请日：2001-12-26
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TAKAHASHI EIJI , FUKUMOTO YUKIHIRO , SAITO YOSHIYUKI , SHIBATA OSAMU , TANIMOTO SHINICHI , NAKAYAMA TAKESHI
IPC分类号： G06F17/50 , H01P1/00 , H05K3/00 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a tamper-proof multilayer substrate without increasing a manufacturing cost. SOLUTION: A signal line, which requires tamper-proof property, is a signal line connecting a terminal 102 and a terminal 115, and the signal line is wired by means of a foil 103, a via 104, a foil 111, a via 105, a foil 112, a via 106 and a foil 113. Any part existing in a surface layer of a wiring of a signal line requiring tamper-proof property is disposed below a component. That is, a component 101 comprises the foil 103 and a tip part of the via 104 in its occupation region. A component 107 comprises the top part of the via 105 in its occupation region. The component 108 comprises the top part of the via 106 in its occupation region. The component 109 comprises the top part of the via 104 in its occupation region. The component 110 comprises the top part of the via 105 in its occupation region. The component 114 comprises the foil 113 and the top part of the via 106 in its occupation region.

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