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1. 发明申请

WO2014100362A1 APPARATUS AND METHOD FOR GENERATING DESCRIPTORS TO TRANSFER DATA TO AND FROM NON-VOLATILE SEMICONDUCTOR MEMORY OF A STORAGE DRIVE 审中-公开
标题翻译：用于生成描述符以传输数据到存储驱动器的非易失性半导体存储器的装置和方法
公开(公告)号：WO2014100362A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/076437
申请日：2013-12-19
申请人： MARVELL WORLD TRADE LTD. , LEE, Chi Kong , AU, Siu-Hung Frederick , PARK, Jungil , SHIN, Hyunsuk , XU, Wei , HE, Jinjin , SUN, Fei
发明人： LEE, Chi Kong , AU, Siu-Hung Frederick , PARK, Jungil , SHIN, Hyunsuk , XU, Wei , HE, Jinjin , SUN, Fei
IPC分类号： G06F3/06 , G06F13/16
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C16/32
摘要： A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory.
摘要翻译：包括第一，第二，第三，第四和第五模块的存储驱动器。第一个模块被配置为控制主机设备和存储驱动器之间的数据块传输。第二模块被配置为将数据块传送到存储驱动器中的非易失性半导体存储器和/或从其移出。第三模块被配置为生成第一描述符，其描述在第二模块和非易失性半导体存储器之间传输数据块。第四模块被配置为根据第一描述符生成第二描述符。每个第二描述符对应于数据块中的相应一个。第五模块被配置为基于第二描述符生成指令信号。第二模块被配置为基于指令信号在第一模块和非易失性半导体存储器之间传送数据块。

2. 发明申请

WO2013138540A1 ARCHITECTURE TO ALLOW EFFICIENT STORAGE OF DATA ON NAND FLASH MEMORY 审中-公开
标题翻译：架构能够有效地存储NAND闪存中的数据
公开(公告)号：WO2013138540A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/031114
申请日：2013-03-14
申请人： MARVELL WORLD TRADE LTD. , AU, Siu-Hung Frederick , SUN, Fei , SHIN, Hyunsuk , LEE, Chi Kong
发明人： AU, Siu-Hung Frederick , SUN, Fei , SHIN, Hyunsuk , LEE, Chi Kong
IPC分类号： G06F11/10 , G06F3/06
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/064 , G06F3/0679 , G06F11/1008 , G06F11/1068 , G06F11/108 , G06F2212/7202 , G06F2212/7208 , Y02D10/13
摘要： Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium. A data stream is received and the data stream is portioned into a plurality of allocation units (AUs), where each AU in the plurality of AUs has a predetermined byte length. A first portion of a selected AU from the plurality of AUs is written to a first page of the plurality of pages and a second portion of the selected AU is written to a second page of the plurality of pages by consecutively writing bytes of the selected AU from a starting byte on the first page to an ending byte on the second page.
摘要翻译：提供了将数据写入存储介质的系统，方法，装置和技术。存储介质的条带经由一个或多个数据传送通道接口，其中条带包括存储介质的多个页面。接收数据流，并将数据流分成多个分配单元（AU），其中多个AU中的每个AU具有预定的字节长度。来自多个AU的所选AU的第一部分被写入多页的第一页，并且所选择的AU的第二部分通过连续写入所选择的AU的字节而被写入多页的第二页从第一页的起始字节到第二页的结束字节。

3. 发明申请

WO2012087971A2 DESCRIPTOR SCHEDULER 审中-公开
公开(公告)号：WO2012087971A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/065913
申请日：2011-12-19
申请人： MARVELL WORLD TRADE LTD. , LEE, Chi Kong , AU, Siu-Hung Fred , PARK, Jungil , SHIN, Hyunsuk
发明人： LEE, Chi Kong , AU, Siu-Hung Fred , PARK, Jungil , SHIN, Hyunsuk
IPC分类号： G06F9/48
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/068 , G06F3/0688
摘要： Methods, systems and computer program products for providing a sequencer that schedules job descriptors are described. The sequencer can manage the scheduling of the job descriptors for execution based on the availability of their respective segments and channels. For example, the sequencer can check the status of the segments, and identify one or more segments that are in busy or full state, or one or more segments that are in non-busy or empty state. Based on the status check, the sequencer can execute job descriptors out of order, and in particular, give priorities to job descriptors whose associated segments are available over job descriptors whose associated segments are in busy or full state. In doing so, pending job descriptors can be processed quicker and unnecessary latency can be avoided.
摘要翻译：描述了用于提供排序作业描述符的排序器的方法，系统和计算机程序产品。定序器可以根据各自片段和通道的可用性来管理作业描述符的调度以供执行。例如，定序器可以检查段的状态，并识别处于繁忙或满状态的一个或多个段或处于非忙或空状态的一个或多个段。基于状态检查，序列发生器可以不按顺序执行作业描述符，并且特别给作业描述符赋予优先级，其作业描述符的相关段可在相关段处于繁忙或满状态的作业描述符上可用。这样做可以更快地处理待处理的作业描述符，避免不必要的延迟。

4. 发明申请

WO2012006062A1 INTERFACE MANAGEMENT CONTROL SYSTEMS AND METHODS FOR NON-VOLATILE SEMICONDUCTOR MEMORY 审中-公开
标题翻译：非易失性半导体存储器的界面管理控制系统和方法
公开(公告)号：WO2012006062A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/042124
申请日：2011-06-28
申请人： MARVELL WORLD TRADE LTD. , LEE, Chi Kong , AU, Siu-Hung Fred , PARK, Jungil , SHIN, Hyunsuk
发明人： LEE, Chi Kong , AU, Siu-Hung Fred , PARK, Jungil , SHIN, Hyunsuk
IPC分类号： G06F13/16 , G11C7/00
CPC分类号： G06F12/0246 , G06F13/1668 , G06F2212/7201
摘要： A control system includes a control module ( 27 ) configured to control data transfer events of blocks of data between an interface management module ( 50 ) and a non-volatile semiconductor memory ( 28 ) based on at least two descriptors ( 84 ) for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive ( 14 ). A command management module ( 60 ) is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals ( 102 ) based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.
摘要翻译：控制系统包括控制模块（27），其被配置为基于至少两个描述符（84）来控制在接口管理模块（50）和非易失性半导体存储器（28）之间的数据块的数据传输事件的数据传输事件。准备非易失性半导体存储器用于数据传输事件的读取事件或程序事件。接口管理模块和非易失性半导体存储器被配置为在固态存储器驱动器（14）内操作。命令管理模块（60）被配置为基于所述至少两个描述符生成参数信号。接口管理模块被配置为基于参数信号产生指令信号（102），并将指令信号发送到非易失性半导体存储器以执行读取事件或程序事件。

5. 发明申请

WO2009039222A2 FLEXIBLE SEQUENCER DESIGN ARCHITECTURE FOR SOLID STATE MEMORY CONTROLLER 审中-公开
标题翻译：用于固态存储器控制器的灵活的定序器设计体系结构
公开(公告)号：WO2009039222A2
公开(公告)日：2009-03-26
申请号：PCT/US2008/076741
申请日：2008-09-17
申请人： MARVELL WORLD TRADE LTD. , SHIN, Hyunsuk , LEE, Chi Kong , YOON, Tony
发明人： SHIN, Hyunsuk , LEE, Chi Kong , YOON, Tony
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F13/1668 , G06F3/061 , G06F3/0659 , G06F3/0688
摘要： A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks.
摘要翻译：一种用于控制对固态存储器设备的访问的方法和设备，其可以允许在固件存储器设备最小干预的情况下访问固态存储器设备的最大并行性。为了减少主机时间的浪费，可以将多个闪存设备连接到每个通道。作业/描述符体系结构可用于通过允许每个存储器设备分开操作来增加并行性。作业可以用来表示读取，写入或擦除操作。当固件想要将作业分配给设备时，它可以发出描述符，其可以包含关于目标通道，目标设备，操作类型等的信息。固件可以提供描述符而不等待来自存储器的响应设备，并且可以连续发布多个作业以形成作业队列。固件完成编程描述符后，序列器可以处理剩余的工作，以便固件可以专注于其他任务。

6. 发明申请

WO2009046115A1 FLASH MEMORY CONTROLLER 审中-公开
标题翻译：闪存控制器
公开(公告)号：WO2009046115A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/078462
申请日：2008-10-01
申请人： MARVELL WORLD TRADE LTD. , YOON, Tony , GOTO, Akio , LEE, Chi Kong , URABE, Masayuki
发明人： YOON, Tony , GOTO, Akio , LEE, Chi Kong , URABE, Masayuki
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F3/0601 , G06F3/0602 , G06F3/0604 , G06F3/0605 , G06F3/061 , G06F3/0622 , G06F3/0628 , G06F3/0653 , G06F3/0659 , G06F13/1689
摘要： Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device.
摘要翻译：描述了用于在一个或多个闪存设备之间实现轮询过程的方法，系统和计算机程序产品。在一些实现中，轮询过程可以包括向闪存设备发送读取状态命令以检测闪存设备的就绪或忙碌状态。闪存装置中可以包括状态寄存器，用于存储表示写入（或擦除）操作的执行状态的状态信号。固态驱动系统可以通过读取闪速存储器件的状态寄存器来执行轮询过程。

7. 发明申请

WO2010027983A1 PROGAMMING DATA INTO A MULTI-PLANE FLASH MEMORY 审中-公开
标题翻译：将数据准备到多平面闪存中
公开(公告)号：WO2010027983A1
公开(公告)日：2010-03-11
申请号：PCT/US2009/055632
申请日：2009-09-01
申请人： MARVELL WORLD TRADE LTD. , GOTO, Akio , LEE, Chi Kong , URABE, Masayuki
发明人： GOTO, Akio , LEE, Chi Kong , URABE, Masayuki
IPC分类号： G11C7/10 , G11C16/10 , G06F13/16
CPC分类号： G11C16/10 , G11C7/10 , G11C2207/2245 , G11C2216/14
摘要： Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane "1") can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.
摘要翻译：用于将数据编程到多平面存储器件中的系统，方法和计算机程序产品采用多平面数据顺序。为了允许编程多个数据页，而不需要增加页缓冲器的大小，在一些实现中，可以操纵数据页被编程的数据传输方案。具体来说，所有通道的数据可以首先被并行编程到多平面闪速存储器件的第一平面中。在进行数据传送程序操作的同时，要编程到后续平面（例如，平面“1”）中的数据可被读入并缓存在一个或多个页面缓冲器中。在第一个平面的数据传输程序完成后，缓存在页面缓冲区中的数据可以立即锁存并编程到多平面闪存设备中。

8. 发明公开

EP2656216A2 DESCRIPTOR SCHEDULER 有权转让
标题翻译：流控制的描述符
公开(公告)号：EP2656216A2
公开(公告)日：2013-10-30
申请号：EP11811236.6
申请日：2011-12-19
申请人： Marvell World Trade Ltd.
发明人： LEE, Chi Kong , AU, Siu-Hung Fred , PARK, Jungil , SHIN, Hyunsuk
IPC分类号： G06F9/48
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/068 , G06F3/0688
摘要： Methods, systems and computer program products for providing a sequencer that schedules job descriptors are described. The sequencer can manage the scheduling of the job descriptors for execution based on the availability of their respective segments and channels. For example, the sequencer can check the status of the segments, and identify one or more segments that are in busy or full state, or one or more segments that are in non-busy or empty state. Based on the status check, the sequencer can execute job descriptors out of order, and in particular, give priorities to job descriptors whose associated segments are available over job descriptors whose associated segments are in busy or full state.

9. 发明授权

EP2347417B1 PROGRAMMING DATA INTO A MULTI-PLANE FLASH MEMORY 有权
标题翻译：将数据编程到多平面闪存中
公开(公告)号：EP2347417B1
公开(公告)日：2018-04-18
申请号：EP09792140.7
申请日：2009-09-01
申请人： Marvell World Trade Ltd.
发明人： GOTO, Akio , LEE, Chi Kong , URABE, Masayuki
IPC分类号： G11C7/10 , G11C16/10 , G06F13/16
CPC分类号： G11C16/10 , G11C7/10 , G11C2207/2245 , G11C2216/14
摘要： Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.

10. 发明公开

EP2347417A1 PROGAMMING DATA INTO A MULTI-PLANE FLASH MEMORY 有权
标题翻译： EINEM MEHREBENEN-FLASH-SPEICHER中的PROGRAMMIEREN VON DATEN
公开(公告)号：EP2347417A1
公开(公告)日：2011-07-27
申请号：EP09792140.7
申请日：2009-09-01
申请人： Marvell World Trade Ltd.
发明人： GOTO, Akio , LEE, Chi Kong , URABE, Masayuki
IPC分类号： G11C7/10 , G11C16/10 , G06F13/16
CPC分类号： G11C16/10 , G11C7/10 , G11C2207/2245 , G11C2216/14
摘要： Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.
摘要翻译：用于将数据编程到多平面存储器件中的系统，方法和计算机程序产品采用多平面数据顺序。为了允许编程多个数据页，而不需要增加页缓冲器的大小，在一些实现中，可以操纵数据页被编程的数据传输方案。具体地说，可以首先将所有通道的数据并行编程到多平面闪速存储器件的第一平面中。在进行数据传送程序操作的同时，要编程到后续平面（例如平面“1”）中的数据可被读入并缓存在一个或多个页缓冲器中。在第一个平面的数据传输程序完成后，缓存在页面缓冲区中的数据可以立即锁存并编程到多平面闪存设备中。

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