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1. 发明授权

US09057760B2 Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures 有权
标题翻译：用于检测集成电路芯片中的结构缺陷的电路，使用和制造方法以及设计结构
公开(公告)号：US09057760B2
公开(公告)日：2015-06-16
申请号：US13010057
申请日：2011-01-20
申请人： Luke D. Lacroix , Mark C. H. Lamorey , Steven F. Oakland , Janak G. Patel , Kerry P. Pfarr , Peter Slota, Jr. , David B. Stone
发明人： Luke D. Lacroix , Mark C. H. Lamorey , Steven F. Oakland , Janak G. Patel , Kerry P. Pfarr , Peter Slota, Jr. , David B. Stone
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2884 , G01R31/2896 , H01L21/76895 , H01L22/32
摘要： Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.
摘要翻译：本文提供了检测电路，使用和制造方法以及设计结构。该结构包括穿过集成电路的一个或多个金属层的至少一个信号线。电路耦合到所述至少一个信号线，其被构造为接收具有来自至少一个信号线的已知信号或来自不同电位的信号的信号，并且基于哪个信号被接收，确定是否存在集成电路中的结构缺陷。

2. 发明授权

US08759977B2 Elongated via structures 有权
标题翻译：通过结构伸长
公开(公告)号：US08759977B2
公开(公告)日：2014-06-24
申请号：US13459785
申请日：2012-04-30
申请人： Luke D. LaCroix , Mark C. H. Lamorey , Janak G. Patel , Peter Slota, Jr. , David B. Stone
发明人： Luke D. LaCroix , Mark C. H. Lamorey , Janak G. Patel , Peter Slota, Jr. , David B. Stone
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/768 , H01L23/5226 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
摘要翻译：集成电路结构包括形成层压结构的多个绝缘体层（彼此连接）。进一步包括在每个绝缘体层内的开口，以及通孔开口内的导电通孔材料。相邻绝缘体层的对应的通孔内的导电通孔材料电连接以形成通过层压结构的顶表面和底表面之间的绝缘体层的连续的电通路。在每个连续的电通路中，通孔相对于彼此定位，以形成通过层压结构的导电过孔材料的对角线结构路径。相邻绝缘体层的相应通孔开始部分重叠。对角结构路径与顶面和底面非垂直。

3. 发明申请

US20130285251A1 ELONGATED VIA STRUCTURES 有权
标题翻译：通过结构延伸
公开(公告)号：US20130285251A1
公开(公告)日：2013-10-31
申请号：US13459785
申请日：2012-04-30
申请人： Luke D. LaCroix , Mark C. H. Lamorey , Janak G. Patel , Peter Slota, JR. , David B. Stone
发明人： Luke D. LaCroix , Mark C. H. Lamorey , Janak G. Patel , Peter Slota, JR. , David B. Stone
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/768 , H01L23/5226 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
摘要翻译：集成电路结构包括形成层叠结构的多个绝缘体层（彼此连接）。进一步包括在每个绝缘体层内的开口，以及通孔开口内的导电通孔材料。相邻绝缘体层的对应的通孔内的导电通孔材料电连接以形成通过层压结构的顶表面和底表面之间的绝缘体层的连续的电通路。在每个连续的电通路中，通孔相对于彼此定位，以形成通过层压结构的导电过孔材料的对角线结构路径。相邻绝缘体层的相应通孔开始部分重叠。对角结构路径与顶面和底面非垂直。

4. 发明授权

US09093445B2 Packaging identical chips in a stacked structure 有权
标题翻译：在堆叠结构中包装相同的芯片
公开(公告)号：US09093445B2
公开(公告)日：2015-07-28
申请号：US13219084
申请日：2011-08-26
申请人： Evan G. Colgan , Luke D. LaCroix , Mark C. H. Lamorey , David B. Stone
发明人： Evan G. Colgan , Luke D. LaCroix , Mark C. H. Lamorey , David B. Stone
IPC分类号： H03K3/00 , H01L23/50 , H01L25/065 , G11C11/4072
CPC分类号： H01L23/50 , G11C11/4072 , H01L25/0657 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/0002 , H03K3/00 , H01L2924/00
摘要： Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
摘要翻译：提供了用于在堆叠结构中包装相同处理的芯片的方法和结构。闩锁链包括与第一芯片相关联的具有单个或多个闩锁的第一闩锁链。第一锁存链被构造成从第一芯片读取数据信息。闩锁链包括具有与第二芯片相关联的单个或多个闩锁的第二闩锁链。第二锁存链被构造成从第二芯片读取数据信息。第一锁存链和第二锁存链彼此连接，使得形成跨越码片边界的单个锁存链。第一锁存链和第二锁存链被构造成分别提供用于识别第一芯片和第二芯片的识别信息。

5. 发明申请

US20130049834A1 PACKAGING IDENTICAL CHIPS IN A STACKED STRUCTURE 有权
标题翻译：在堆叠结构中包装标识牌
公开(公告)号：US20130049834A1
公开(公告)日：2013-02-28
申请号：US13219084
申请日：2011-08-26
申请人： Evan G. Colgan , Luke D. LaCroix , Mark C. H. Lamorey , David B. Stone
发明人： Evan G. Colgan , Luke D. LaCroix , Mark C. H. Lamorey , David B. Stone
IPC分类号： H03K3/00
CPC分类号： H01L23/50 , G11C11/4072 , H01L25/0657 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/0002 , H03K3/00 , H01L2924/00
摘要： Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
摘要翻译：提供了用于在堆叠结构中包装相同处理的芯片的方法和结构。闩锁链包括与第一芯片相关联的具有单个或多个闩锁的第一闩锁链。第一锁存链被构造成从第一芯片读取数据信息。闩锁链包括具有与第二芯片相关联的单个或多个闩锁的第二闩锁链。第二锁存链被构造成从第二芯片读取数据信息。第一锁存链和第二锁存链彼此连接，使得形成跨越码片边界的单个锁存链。第一锁存链和第二锁存链被构造成分别提供用于识别第一芯片和第二芯片的识别信息。

6. 发明授权

US09245083B2 Method, structures and method of designing reduced delamination integrated circuits 有权
标题翻译：减少分层集成电路的设计方法，结构和方法
公开(公告)号：US09245083B2
公开(公告)日：2016-01-26
申请号：US13272395
申请日：2011-10-13
申请人： Mark C. H. Lamorey , David B. Stone
发明人： Mark C. H. Lamorey , David B. Stone
IPC分类号： H01L23/48 , G06F17/50 , H01L21/768 , H01L23/522
CPC分类号： G06F17/5077 , H01L21/76883 , H01L23/522 , H01L2224/11 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels.
摘要翻译：集成电路线结构。该结构包括半导体衬底上的一组互连电平，该组互连电平的每个互连电平包括嵌入在层间电介质层中的操作线; 在所述一组互连级别的最上层互连层上的绝缘阻挡层和所述钝化层上的接合焊盘; 围绕所述焊盘的周边并延伸到所述一组互连级别的应力减小区; 在应力减小区域中的每个互连级别中的细长填充线，所述细长填充线不连接到任何非接地操作线; 并且每组互连级别的每个互连级别的细长填充线物理地连接到该组填充级别的立即上部和下部互连级别的细长填充线。

7. 发明授权

US09006739B2 Semiconductor test and monitoring structure to detect boundaries of safe effective modulus 有权
公开(公告)号：US09006739B2
公开(公告)日：2015-04-14
申请号：US13448775
申请日：2012-04-17
申请人： James V. Crain, Jr. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
发明人： James V. Crain, Jr. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
IPC分类号： H01L21/66 , H01L23/522 , H01L23/00
CPC分类号： H01L22/34 , G01R31/2601 , G01R31/2607 , H01L23/522 , H01L24/13 , H01L24/14 , H01L2224/13111 , H01L2224/14131 , H01L2224/14515 , H01L2924/01029 , H01L2924/01047 , H01L2924/01051 , H01L2924/01082 , H01L2924/01083 , H01L2924/14
摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

8. 发明申请

US20130270558A1 SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS 有权
公开(公告)号：US20130270558A1
公开(公告)日：2013-10-17
申请号：US13448775
申请日：2012-04-17
申请人： James V. Crain, JR. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
发明人： James V. Crain, JR. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
IPC分类号： H01L23/498 , H01L21/66
CPC分类号： H01L22/34 , G01R31/2601 , G01R31/2607 , H01L23/522 , H01L24/13 , H01L24/14 , H01L2224/13111 , H01L2224/14131 , H01L2224/14515 , H01L2924/01029 , H01L2924/01047 , H01L2924/01051 , H01L2924/01082 , H01L2924/01083 , H01L2924/14
摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

9. 发明申请

US20150206835A1 METHOD, STRUCTURES AND METHOD OF DESIGNING REDUCED DELAMINATION INTEGRATED CIRCUITS 有权
标题翻译：方法，结构和设计减少分层集成电路的方法
公开(公告)号：US20150206835A1
公开(公告)日：2015-07-23
申请号：US13272395
申请日：2011-10-13
申请人： Mark C. H. Lamorey , David B. Stone
发明人： Mark C. H. Lamorey , David B. Stone
IPC分类号： H01L23/528 , G06F17/50 , H01L21/768
CPC分类号： G06F17/5077 , H01L21/76883 , H01L23/522 , H01L2224/11 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels.
摘要翻译：集成电路线结构。该结构包括半导体衬底上的一组互连电平，该组互连电平的每个互连电平包括嵌入在层间电介质层中的操作线; 在所述一组互连级别的最上层互连层上的绝缘阻挡层和所述钝化层上的接合焊盘; 围绕所述焊盘的周边并延伸到所述一组互连级别的应力减小区; 在应力减小区域中的每个互连级别中的细长填充线，所述细长填充线不连接到任何非接地操作线; 并且每组互连级别的每个互连级别的细长填充线物理地连接到该组填充级别的立即上部和下部互连级别的细长填充线。

10. 发明授权

US08796133B2 Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections 有权
标题翻译：在控制崩溃芯片连接下用于防止电介质裂纹的优化金属化
公开(公告)号：US08796133B2
公开(公告)日：2014-08-05
申请号：US13553941
申请日：2012-07-20
申请人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C. H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
发明人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C. H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/53295 , H01L23/3192 , H01L23/522 , H01L23/5329 , H01L2224/0401 , H01L2224/05 , H01L2224/05567 , H01L2224/05572 , H01L2224/13 , H01L2224/13021 , H01L2924/00014 , H01L2924/3512 , H01L2224/05552
摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.
摘要翻译：一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。衬底包括用于C4的多个附接垫。该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

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