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1. 发明授权

US5644529A Integrated circuit for the programming of a memory cell in a non-volatile memory register 失效
标题翻译：用于编程非易失性存储器寄存器中的存储单元的集成电路
公开(公告)号：US5644529A
公开(公告)日：1997-07-01
申请号：US635455
申请日：1996-04-18
申请人： Luigi Pascucci , Silvia Padoan
发明人： Luigi Pascucci , Silvia Padoan
IPC分类号： G11C17/00 , G11C16/06 , G11C16/12 , G11C29/00 , G11C29/04 , G11C29/12 , G11C11/40
CPC分类号： G11C29/789 , G11C16/12 , G11C29/12
摘要： In an integrated circuit for programming a memory cell in a non-volatile memory register which is associated with a memory matrix wherein the non-volatile memory register is used to store a redundancy address, the memory cell has at least one programmable non-volatile memory element having a control electrode and a data electrode and is suitable to store one bit of information. A load circuit associated to the memory element reads the information stored therein. The integrated circuit has switching means connected in series between the data electrode and a respective address signal line of an address signal bus which also supplies a decoding circuitry of the memory matrix. The switching means are controlled by a signal which determines the switching means to electrically connect the data electrode of the memory element to the address signal line when the memory cell of the non-volatile memory register is to be programmed, and to electrically disconnect the data electrode of the memory element from the address signal line when the information stored in the memory element is to be read by the load circuit.
摘要翻译：在用于对与非易失性存储器寄存器用于存储冗余地址的存储器矩阵相关联的非易失性存储器寄存器中的存储器单元进行编程的集成电路中，存储器单元具有至少一个可编程非易失性存储器元件具有控制电极和数据电极，并且适合于存储一位信息。与存储器元件相关联的负载电路读取存储在其中的信息。集成电路具有串联连接在数据电极和还提供存储器矩阵的解码电路的地址信号总线的相应地址信号线之间的开关装置。开关装置由确定开关装置的信号控制，当非易失性存储寄存器的存储单元要被编程时，切换装置将存储元件的数据电极电连接到地址信号线，并且电连接数据当存储在存储元件中的信息要由负载电路读取时，来自地址信号线的存储元件的电极。

2. 发明授权

US5768115A Voltage booster with an acceleration circuit 失效
标题翻译：带加速电路的升压器
公开(公告)号：US5768115A
公开(公告)日：1998-06-16
申请号：US855922
申请日：1997-05-14
申请人： Luigi Pascucci , Silvia Padoan , Carla Maria Golla
发明人： Luigi Pascucci , Silvia Padoan , Carla Maria Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , H02M3/07 , H02M3/18 , G05F1/40
CPC分类号： H02M3/07 , G11C5/145
摘要： A voltage booster comprising a charge pump for generating a boost voltage over a boost line. The booster comprises a comparator which is supplied by a voltage divider with a voltage proportional to the boost voltage, and by a reference source with a low reference voltage, and which, depending on the outcome of the comparison, enables or disables the charge pump. A voltage limiter is connected between the boost line and ground; and a acceleration circuit accelerates the voltage increase on the acceleration line following low-power operation in which the paths toward ground are interrupted for reducing consumption.
摘要翻译：一种升压器，包括用于在升压线上产生升压电压的电荷泵。升压器包括由分压器提供的具有与升压电压成比例的电压的比较器和具有低参考电压的参考源，并且根据比较的结果，启用或禁用电荷泵。升压线和地之间连接一个限压器; 并且加速电路在低功率运行之后加速加速线上的电压增加，其中朝向地面的路径被中断以减少消耗。

3. 发明授权

US5650671A Charge pump circuit 失效
标题翻译：电荷泵电路
公开(公告)号：US5650671A
公开(公告)日：1997-07-22
申请号：US379689
申请日：1995-01-27
申请人： Luigi Pascucci , Marco Maccarrone , Silvia Padoan
发明人： Luigi Pascucci , Marco Maccarrone , Silvia Padoan
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , H02M3/07 , H02M3/18
CPC分类号： H02M3/07 , G11C5/145
摘要： A charge pump circuit including a number of pull-up stages connected in parallel with one another between a reference potential line and an output line. Each stage includes a capacitor having a first terminal connected to a charging and discharging node, and a second terminal connected to a pull-up node for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node is connected to the supply line via a charging transistor having a control terminal connected to a high-voltage bias node formed by the adjacent stage in the opposite operating phase, for charging the capacitor substantially up to the supply voltage.
摘要翻译：一种电荷泵电路，包括在参考电位线和输出线之间彼此并联连接的多个上拉级。每个级包括具有连接到充电和放电节点的第一端子的电容器，以及连接到上拉节点的第二端子，用于在第一充电操作阶段和第二充电转移操作阶段之间切换。充电和放电节点通过充电晶体管连接到电源线，该充电晶体管具有在相反的工作阶段中由相邻级形成的高压偏置节点连接的控制端子，用于对电容器充电至基本上达到电源电压。

4. 发明授权

US5548554A Integrated programming circuitry for an electrically programmable semiconductor memory device with redundancy 失效
标题翻译：用于具有冗余的电可编程半导体存储器件的集成编程电路
公开(公告)号：US5548554A
公开(公告)日：1996-08-20
申请号：US365154
申请日：1994-12-28
申请人： Luigi Pascucci , Silvia Padoan , Marco Maccarrone
发明人： Luigi Pascucci , Silvia Padoan , Marco Maccarrone
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/70
摘要： An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits, each one associated with a respective memory matrix portion or group of columns, and a plurality of programming load control circuits, each one controlling the activation of one respective programming load circuit according to the logic state of a respective data line carrying a datum to be programmed; the memory device comprises a group of redundancy bit lines and an associated redundancy programming load circuit; each programming load control circuit comprises decoding means supplied with signals which, when a defective column address is supplied to the memory device during programming, are generated from a matrix portion identifying code stored in a non-volatile register wherein the defective column address is stored, and switch means responsive to a decoded signal at the output of said decoding means to enable the activation of the redundancy programming load circuit according to the logic state of the data signal line and to cause the inhibition of the activation of the respective programming load circuit.
摘要翻译：用于电可编程半导体存储器件的集成编程电路包括多个编程负载电路，每个编程负载电路各自与相应的存储器矩阵部分或一组列相关联，以及多个编程负载控制电路，每个编程负载控制电路控制一个相应的激活根据携带要编程的数据的相应数据线的逻辑状态编程负载电路; 存储器件包括一组冗余位线和相关的冗余编程负载电路; 每个编程负载控制电路包括提供有信号的解码装置，当在编程期间将缺陷列地址提供给存储器件时，从存储在存储有缺陷列地址的非易失性寄存器中的矩阵部分识别代码生成信号，以及响应于所述解码装置的输出处的解码信号的开关装置，以使能根据数据信号线的逻辑状态激活冗余编程负载电路，并且导致禁止各个编程负载电路的激活。

5. 发明授权

US5687124A Circuit for identifying a memory cell having erroneous data stored therein 失效
标题翻译：用于识别其中存储有错误数据的存储单元的电路
公开(公告)号：US5687124A
公开(公告)日：1997-11-11
申请号：US521304
申请日：1995-08-30
申请人： Carla Golla , Silvia Padoan , Luigi Pascucci
发明人： Carla Golla , Silvia Padoan , Luigi Pascucci
IPC分类号： G11C17/00 , G11C7/00 , G11C16/02 , G11C16/34
CPC分类号： G11C16/3486 , G11C16/3459 , G11C16/3468
摘要： A circuit for selectively programming a single bit in non-volatile memory is disclosed. The circuit consists of at least one comparator, at least one transistor, and at least one logic gate for each elementary memory in the memory word. In operation, the circuit allows for individual correction of mis-programmed cells within the memory by comparing the actual contents of the memory with the desired contents. If the actual contents does not match the desired contents, that individual cell is re-programmed.
摘要翻译：公开了一种用于在非易失性存储器中选择性地编程单个位的电路。电路由至少一个比较器，至少一个晶体管和至少一个逻辑门组成，用于存储器字中的每个基本存储器。在操作中，电路允许通过将存储器的实际内容与期望的内容进行比较来对存储器内的错误编程的单元进行单独校正。如果实际内容与所需内容不匹配，那么该单个单元格将被重新编程。

6. 发明授权

US5559449A Programmable logic array structure for semiconductor nonvolatile memories, particularly flash-eeproms 失效
标题翻译：用于半导体非易失性存储器的可编程逻辑阵列结构，特别是闪存
公开(公告)号：US5559449A
公开(公告)日：1996-09-24
申请号：US391149
申请日：1995-02-21
申请人： Silvia Padoan , Luigi Pascucci
发明人： Silvia Padoan , Luigi Pascucci
IPC分类号： G11C17/00 , G11C16/06 , H01L27/10 , H03K19/177 , H03K19/173
CPC分类号： H03K19/1772
摘要： The PLA, which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator which generates a monostable succession of read enabling signals on receiving a predetermined switching edge of an external clock signal. The clock generator enables evaluation of the AND and OR planes of the PLA and subsequently storage of the results through sections duplicating the propagation delays of the signals in the corresponding parts of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.
摘要翻译：实现非易失性存储器的状态机的PLA呈现动态NAND非NOT-NOR配置，并且用于正确读取PLA的定时信号由时钟发生器产生，时钟发生器在接收时产生单个可读序列的读使能信号外部时钟信号的预定开关沿。时钟发生器可以评估PLA的AND和OR平面，然后通过复制PLA中相应部分的信号的传播延迟的部分来存储结果。一旦完成存储步骤，阅读就会被终止，因此只要严格必要时，解放军的阅读时间就会持续下去，从而防止错误切换，同时确保PLA的正确阅读。

7. 发明授权

US5532972A Method and circuit for timing the reading of nonvolatile memories 失效
标题翻译：用于定时读取非易失性存储器的方法和电路
公开(公告)号：US5532972A
公开(公告)日：1996-07-02
申请号：US391920
申请日：1995-02-21
申请人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
发明人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C7/22 , G11C16/02 , G11C16/32 , G11C7/00
CPC分类号： G11C7/02 , G11C16/32 , G11C7/1006 , G11C7/22
摘要： A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.
摘要翻译：电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。

8. 发明授权

US5748548A Device for detecting a reduction in a supply voltage 失效
公开(公告)号：US5748548A
公开(公告)日：1998-05-05
申请号：US711132
申请日：1996-09-09
申请人： Silvia Padoan , Marco Olivo , Carla Golla
发明人： Silvia Padoan , Marco Olivo , Carla Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C11/407
CPC分类号： G11C5/143 , G11C16/30 , G11C5/147
摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

9. 发明授权

US5617356A Regulation circuit and method for the erasing phase of non-volatile memory cells 失效
标题翻译：非易失性存储单元擦除阶段的调节电路和方法
公开(公告)号：US5617356A
公开(公告)日：1997-04-01
申请号：US395361
申请日：1995-02-21
申请人： Carla Golla , Silvia Padoan , Marco Olivo
发明人： Carla Golla , Silvia Padoan , Marco Olivo
IPC分类号： G11C17/00 , G11C16/06 , G11C16/14 , G11C16/16 , G11C16/02
CPC分类号： G11C16/16 , G11C16/14
摘要： A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.
摘要翻译：一种用于对电可编程存储器件中的非易失性存储单元进行放电的调节电路，该电路包括连接在编程电压基准和由形成所述存储单元的晶体管的源极端子共享的线之间的至少一个开关，所述公共线与源极端子之间的至少一个放电连接和接地电压基准，还包括与电流发生器连接的线路的第二连接点和常开开关。还提供了连接到线路的逻辑电路，用于将存在于其上的电压值与预定值进行比较，并输出用于使开关产生的控制信号。该解决方案允许在擦除阶段结束时实现线路的缓慢放电阶段。

10. 发明授权

US5583820A Device for detecting a reduction in a supply voltage 失效
标题翻译：用于检测电源电压降低的装置
公开(公告)号：US5583820A
公开(公告)日：1996-12-10
申请号：US366211
申请日：1994-12-29
申请人： Silvia Padoan , Marco Olivo , Carla Golla
发明人： Silvia Padoan , Marco Olivo , Carla Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C11/407
CPC分类号： G11C5/143 , G11C16/30 , G11C5/147
摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.
摘要翻译：一种电路，用于检测在提供给集成到半导体中的存储装置的电源电压中的阈值以下。比较器耦合在电源线和信号地之间，并具有第一或参考输入和第二或测试信号输入。稳定电压基准的发生器具有耦合到第一输入的输出和耦合到比较器的第二输入的电源电压的分压器。电路装置被布置成以较高的电源电压和还提供给存储装置的编程电压来馈送电源。

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