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1. 发明授权

US5748548A Device for detecting a reduction in a supply voltage 失效
公开(公告)号：US5748548A
公开(公告)日：1998-05-05
申请号：US711132
申请日：1996-09-09
申请人： Silvia Padoan , Marco Olivo , Carla Golla
发明人： Silvia Padoan , Marco Olivo , Carla Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C11/407
CPC分类号： G11C5/143 , G11C16/30 , G11C5/147
摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

2. 发明授权

US5617356A Regulation circuit and method for the erasing phase of non-volatile memory cells 失效
标题翻译：非易失性存储单元擦除阶段的调节电路和方法
公开(公告)号：US5617356A
公开(公告)日：1997-04-01
申请号：US395361
申请日：1995-02-21
申请人： Carla Golla , Silvia Padoan , Marco Olivo
发明人： Carla Golla , Silvia Padoan , Marco Olivo
IPC分类号： G11C17/00 , G11C16/06 , G11C16/14 , G11C16/16 , G11C16/02
CPC分类号： G11C16/16 , G11C16/14
摘要： A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.
摘要翻译：一种用于对电可编程存储器件中的非易失性存储单元进行放电的调节电路，该电路包括连接在编程电压基准和由形成所述存储单元的晶体管的源极端子共享的线之间的至少一个开关，所述公共线与源极端子之间的至少一个放电连接和接地电压基准，还包括与电流发生器连接的线路的第二连接点和常开开关。还提供了连接到线路的逻辑电路，用于将存在于其上的电压值与预定值进行比较，并输出用于使开关产生的控制信号。该解决方案允许在擦除阶段结束时实现线路的缓慢放电阶段。

3. 发明授权

US5583820A Device for detecting a reduction in a supply voltage 失效
标题翻译：用于检测电源电压降低的装置
公开(公告)号：US5583820A
公开(公告)日：1996-12-10
申请号：US366211
申请日：1994-12-29
申请人： Silvia Padoan , Marco Olivo , Carla Golla
发明人： Silvia Padoan , Marco Olivo , Carla Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C11/407
CPC分类号： G11C5/143 , G11C16/30 , G11C5/147
摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.
摘要翻译：一种电路，用于检测在提供给集成到半导体中的存储装置的电源电压中的阈值以下。比较器耦合在电源线和信号地之间，并具有第一或参考输入和第二或测试信号输入。稳定电压基准的发生器具有耦合到第一输入的输出和耦合到比较器的第二输入的电源电压的分压器。电路装置被布置成以较高的电源电压和还提供给存储装置的编程电压来馈送电源。

4. 发明授权

US5519656A Voltage regulator for programming non-volatile and electrically programmable memory cells 失效
标题翻译：用于编程非易失性和电可编程存储单元的电压调节器
公开(公告)号：US5519656A
公开(公告)日：1996-05-21
申请号：US366259
申请日：1994-12-29
申请人： Marco Maccarrone , Marco Olivo , Carla Golla , Silvia Padoan
发明人： Marco Maccarrone , Marco Olivo , Carla Golla , Silvia Padoan
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C7/00
CPC分类号： G11C16/30 , G11C5/147
摘要： A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed back to said input through a current mirror, and a source-follower transistor controlled by the output and connected to the cells through a programming line. Also provided is a MOS transistor which connects to ground the programming line and a corresponding resistive path connected between the current mirror and the second voltage reference.
摘要翻译：一种用于编程非易失性存储单元的电压调节器，其包括在第一和第二参考电压之间供电的放大器级，并且具有连接到第一参考电压的电阻分压器的第一输入端和反馈到所述第一参考电压的输出端通过电流镜输入，源极跟随器晶体管由输出端控制，并通过编程线与单元连接。还提供了连接到编程线的接地的MOS晶体管和连接在电流镜与第二参考电压之间的相应的电阻路径。

5. 发明授权

US06392469B1 Stable reference voltage generator circuit 失效
标题翻译：稳定的参考电压发生器电路
公开(公告)号：US06392469B1
公开(公告)日：2002-05-21
申请号：US08347788
申请日：1994-11-30
申请人： Silvia Padoan , Carla Golla
发明人： Silvia Padoan , Carla Golla
IPC分类号： G05F110
CPC分类号： G05F3/245
摘要： A circuit for generating a stable reference voltage (Vref) as temperature and process parameters vary, including at least one field-effect transistor (M1) and an associated resistive bias element (R) connected in series between a supply voltage (Vcc) and ground (GND), further includes a second field-effect transistor (M2) connected to the first transistor such that the reference voltage (Vref) can be picked up as the difference between the respective threshold voltages of the two transistors. This provides a reference voltage which is uniquely stable against variations in temperature and process parameters.
摘要翻译：用于产生作为温度和过程参数的稳定参考电压（Vref）的电路变化，包括串联连接在电源电压（Vcc）和地之间的至少一个场效应晶体管（M1）和相关联的电阻偏置元件（R）（GND），还包括连接到第一晶体管的第二场效应晶体管（M2），使得可以拾取参考电压（Vref）作为两个晶体管的各个阈值电压之间的差。这提供了对温度和工艺参数变化独特稳定的参考电压。

6. 发明授权

US5687124A Circuit for identifying a memory cell having erroneous data stored therein 失效
标题翻译：用于识别其中存储有错误数据的存储单元的电路
公开(公告)号：US5687124A
公开(公告)日：1997-11-11
申请号：US521304
申请日：1995-08-30
申请人： Carla Golla , Silvia Padoan , Luigi Pascucci
发明人： Carla Golla , Silvia Padoan , Luigi Pascucci
IPC分类号： G11C17/00 , G11C7/00 , G11C16/02 , G11C16/34
CPC分类号： G11C16/3486 , G11C16/3459 , G11C16/3468
摘要： A circuit for selectively programming a single bit in non-volatile memory is disclosed. The circuit consists of at least one comparator, at least one transistor, and at least one logic gate for each elementary memory in the memory word. In operation, the circuit allows for individual correction of mis-programmed cells within the memory by comparing the actual contents of the memory with the desired contents. If the actual contents does not match the desired contents, that individual cell is re-programmed.
摘要翻译：公开了一种用于在非易失性存储器中选择性地编程单个位的电路。电路由至少一个比较器，至少一个晶体管和至少一个逻辑门组成，用于存储器字中的每个基本存储器。在操作中，电路允许通过将存储器的实际内容与期望的内容进行比较来对存储器内的错误编程的单元进行单独校正。如果实际内容与所需内容不匹配，那么该单个单元格将被重新编程。

7. 发明授权

US5600594A Threshold voltage measuring device for memory cells 失效
标题翻译：用于存储单元的阈值电压测量装置
公开(公告)号：US5600594A
公开(公告)日：1997-02-04
申请号：US412326
申请日：1995-03-31
申请人： Silvia Padoan , Marco Maccarrone , Marco Olivo
发明人： Silvia Padoan , Marco Maccarrone , Marco Olivo
IPC分类号： G11C17/00 , G11C29/00 , G11C29/50 , G11C29/56 , G11C16/02
CPC分类号： G11C29/50004 , G11C29/50 , G06F2201/81 , G11C16/04
摘要： A circuit device for measuring the threshold voltage distribution among electrically programmable, non-volatile memory cells, which device comprises a differential amplifier having a first input connected to a first circuit leg including at least one memory cell and a second input connected to a second or reference circuit leg, and circuit means effective to cause an unbalance in the values of the currents flowing in the reference leg. The device is connected between a first supply voltage reference and a second voltage reference, and said circuit means comprise a generator of a varying current as a function of the supply voltage which is associated with the reference leg.
摘要翻译：一种用于测量电可编程，非易失性存储单元之间的阈值电压分布的电路装置，该装置包括差分放大器，该差分放大器具有连接到包括至少一个存储单元的第一电路支路的第一输入端和连接到第二或参考电路支路和电路装置有效地引起在参考支路中流动的电流值的不平衡。该设备连接在第一电源参考电压和第二参考电压之间，并且所述电路装置包括作为与参考支路相关联的电源电压的函数的变化电流的发电机。

8. 发明授权

US5627790A Reading circuit for an integrated semiconductor memory device 失效
标题翻译：集成半导体存储器件的读取电路
公开(公告)号：US5627790A
公开(公告)日：1997-05-06
申请号：US408589
申请日：1995-03-22
申请人： Carla M. Golla , Marco Olivo , Silvia Padoan
发明人： Carla M. Golla , Marco Olivo , Silvia Padoan
IPC分类号： G11C11/409 , G11C7/00 , G11C7/14 , G11C16/06 , G11C16/28 , G11C7/02
CPC分类号： G11C7/14 , G11C16/28
摘要： A device including a load connected by a selection circuit to a number of bit lines, and a load connected to a reference cell, for detecting the current in the selected bit line and in the reference cell. The load connected to the bit lines comprises a transistor, and the reference load comprises two current paths, each formed by one transistor. One of the two transistors is diode-connected, and the other is switchable by a switching network connected to the gate terminal of the respective transistor, for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.
摘要翻译：一种包括通过选择电路连接到多个位线的负载的设备，以及连接到参考单元的负载，用于检测所选位线和参考单元中的电流。连接到位线的负载包括晶体管，并且参考负载包括两个电流路径，每个由一个晶体管形成。两个晶体管中的一个是二极管连接的，另一个晶体管可以由连接到相应晶体管的栅极端子的开关网络切换，以便在仅使能一个参考电流路径时将其关断，并且用于二极管连接当两个参考电流路径都要使能时。

9. 发明授权

US5586077A Circuit device and corresponding method for resetting non-volatile and electrically programmable memory devices 失效
标题翻译：用于复位非易失性和电可编程存储器件的电路器件和相应的方法
公开(公告)号：US5586077A
公开(公告)日：1996-12-17
申请号：US366212
申请日：1994-12-29
申请人： Marco Olivo , Silvia Padoan
发明人： Marco Olivo , Silvia Padoan
IPC分类号： G11C17/00 , G06F1/24 , G11C16/06 , G11C16/30 , G11C7/00
CPC分类号： G11C16/30
摘要： A method for generating a reset signal in an electrically programmable non-volatile storage device of a type which comprises a matrix of memory cells and a control logic portion being supplied a supply voltage and a programming voltage, and a threshold detection circuit adapted to detect a decrease in the supply voltage, provides for the signal applied to the control logic to be obtained as a change-over function between the output signal from the threshold detector and a reset signal generated during the power-on transient of the device.
摘要翻译：一种用于在电可编程非易失性存储装置中产生复位信号的方法，该方法包括存储单元矩阵和提供电源电压和编程电压的控制逻辑部分，以及阈值检测电路，降低电源电压，提供作为在来自阈值检测器的输出信号与在器件的上电瞬变期间产生的复位信号之间的转换功能而获得的控制逻辑的信号。

10. 发明授权

US5532972A Method and circuit for timing the reading of nonvolatile memories 失效
标题翻译：用于定时读取非易失性存储器的方法和电路
公开(公告)号：US5532972A
公开(公告)日：1996-07-02
申请号：US391920
申请日：1995-02-21
申请人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
发明人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C7/22 , G11C16/02 , G11C16/32 , G11C7/00
CPC分类号： G11C7/02 , G11C16/32 , G11C7/1006 , G11C7/22
摘要： A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.
摘要翻译：电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。

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