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1. 发明授权

US09389999B2 System and method for emulating an EEPROM in a non-volatile memory device 有权
标题翻译：用于在非易失性存储器件中仿真EEPROM的系统和方法
公开(公告)号：US09389999B2
公开(公告)日：2016-07-12
申请号：US13587993
申请日：2012-08-17
申请人： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Edvin Paparisto , Thomas Nirschl
发明人： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Edvin Paparisto , Thomas Nirschl
IPC分类号： G06F12/00 , G06F12/02 , G11C16/10
CPC分类号： G06F12/0246 , G06F2212/1044 , G06F2212/7202 , G11C16/105
摘要： The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.
摘要翻译：本发明涉及一种电子存储器系统，更具体地说，涉及用于在非易失性存储器件中仿真电可擦除可编程只读存储器的系统，以及一种以非易失性存储器模拟电可擦除可编程只读存储器的方法存储设备。根据实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，该系统包括闪存，其中闪存可配置成第一区域和第二区域，其中第一区域适于存储第一类数据和第二区域适于存储第二种不同类别的数据。

2. 发明申请

US20140052896A1 SYSTEM AND METHOD FOR EMULATING AN EEPROM IN A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：用于在非易失性存储器件中仿真EEPROM的系统和方法
公开(公告)号：US20140052896A1
公开(公告)日：2014-02-20
申请号：US13587993
申请日：2012-08-17
申请人： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Edvin Paparisto , Thomas Nirschl
发明人： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Edvin Paparisto , Thomas Nirschl
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/1044 , G06F2212/7202 , G11C16/105
摘要： The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.
摘要翻译：本发明涉及一种电子存储器系统，更具体地说，涉及用于在非易失性存储器件中仿真电可擦除可编程只读存储器的系统，以及一种以非易失性存储器模拟电可擦除可编程只读存储器的方法存储设备。根据实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，该系统包括闪存，其中闪存可配置成第一区域和第二区域，其中第一区域适于存储第一类数据和第二区域适于存储第二种不同类别的数据。

3. 再颁专利

USRE39124E1 Integrated circuit having capacitive elements 有权
公开(公告)号：USRE39124E1
公开(公告)日：2006-06-13
申请号：US10625706
申请日：2003-07-23
申请人： Thomas Ehben , Thomas Steinecke , Jens Rosenbusch
发明人： Thomas Ehben , Thomas Steinecke , Jens Rosenbusch
IPC分类号： H01L29/00 , H01L29/94 , H01L31/119 , H01L27/108 , H01L29/76
CPC分类号： H01L23/5223 , H01L23/5222 , H01L23/66 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is configured as a high frequency-optimized capacitance and is distinguished by an extremely low sheet resistance, is connected in parallel with the MOS capacitances. By connecting the areally highly effective MOS capacitance, which, however, is connected with a somewhat higher impedance, in parallel with areally less effective metal capacitances, which, however, are connected to the supply voltage in a very low-impedance manner, it is possible to obtain broadband buffering and thus decoupling of high-frequency interference signals. Very high-frequency interference components are attenuated on the chip and do not pass into the system surrounding the integrated circuit.

4. 发明授权

US06998874B2 Method and apparatus for the transmission of differential signals 有权
公开(公告)号：US06998874B2
公开(公告)日：2006-02-14
申请号：US10093721
申请日：2002-03-08
申请人： Franz Renner , Jens Rosenbusch
发明人： Franz Renner , Jens Rosenbusch
IPC分类号： H03K19/0175
CPC分类号： H04L25/028 , H04L25/0266 , H04L25/0272
摘要： A method is described for transmitting signals on a pair of lines, whereby the signals pass alternately from a low level to a high level. The signals on one line of the pair transmit a complementary level of signals to the other line of the pair, whereby signal drivers are used in a manner to affect an exchange in the levels of the transmitted signals. First, the signal drivers that send complementary levels of signals to the two lines are isolated from the lines. Second, the lines are short-circuited so that an identical intermediary potential between the low-level and the high-level signal, is applied. Third, the short-circuit is removed and the signal drivers are connected so that inversely complementary levels of signals can be sent to both lines.

5. 发明申请

US20140075093A1 METHOD AND SYSTEM FOR IMPLICIT OR EXPLICIT ONLINE REPAIR OF MEMORY 审中-公开
标题翻译：隐含或明示在线修复记忆的方法和系统
公开(公告)号：US20140075093A1
公开(公告)日：2014-03-13
申请号：US13612097
申请日：2012-09-12
申请人： Robert Wiesner , Rudolf Ullmann , Walter Mischo , Jens Rosenbusch
发明人： Robert Wiesner , Rudolf Ullmann , Walter Mischo , Jens Rosenbusch
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F12/0246 , G06F2212/7202 , G11C11/41 , G11C29/4401 , G11C29/76 , G11C29/82 , G11C2029/0409
摘要： Systems and methods related to a memory device are provided. The systems and methods include using at least one driver with predetermined reduced driving capability to drive at least one of the memory elements of the memory device in a reliable detection algorithm. The at least one driver has reduced driving capability compared to a driver used for standard read access. The reliable detection algorithm can include detecting failing memory elements on a respective reading current diverging from an expected or expectable reading current.
摘要翻译：提供了与存储器件相关的系统和方法。该系统和方法包括使用至少一个具有预定的降低驱动能力的驱动器，以可靠的检测算法来驱动存储器件的至少一个存储元件。与用于标准读取访问的驱动程序相比，至少一个驱动器具有降低的驱动能力。可靠的检测算法可以包括在从预期或期望的读取电流分歧的相应读取电流上检测故障存储器元件。

6. 发明授权

US06351147B1 Configuration and method for matching output drivers of integrated circuits to specified conditions 有权
标题翻译：将集成电路的输出驱动器与指定条件进行匹配的配置和方法
公开(公告)号：US06351147B1
公开(公告)日：2002-02-26
申请号：US09199848
申请日：1998-11-25
申请人： Franz Renner , Jens Rosenbusch
发明人： Franz Renner , Jens Rosenbusch
IPC分类号： H03K190175
CPC分类号： G05B19/0423 , G05B2219/21156 , G05B2219/23265 , G05B2219/23399
摘要： A configuration and a method for matching output drivers of integrated circuits to specified conditions include parameters to be taken into account when matching output drivers and/or control signals based on the parameters for matching the output drivers, to be provided in digital form. The configuration and method may additionally or alternatively perform matching by taking into account a level or waveform of a supply voltage of an integrated circuit and/or a technology used in the integrated circuit and/or technical data on a load to be driven and/or demands placed on the output drivers by the load to be driven.
摘要翻译：用于将集成电路的输出驱动器与指定条件相匹配的配置和方法包括在以数字形式提供时，基于用于匹配输出驱动器的参数来匹配输出驱动器和/或控制信号时要考虑的参数。配置和方法可以通过考虑集成电路的电源电压和/或集成电路中使用的技术的电平或波形和/或要驱动的负载的技术数据和/或由驱动的负载对输出驱动器的要求。

7. 发明授权

US06465868B1 Integrated circuit having capacitive elements 有权
标题翻译：具有电容元件的集成电路
公开(公告)号：US06465868B1
公开(公告)日：2002-10-15
申请号：US09640150
申请日：2000-08-16
申请人： Thomas Ehben , Thomas Steinecke , Jens Rosenbusch
发明人： Thomas Ehben , Thomas Steinecke , Jens Rosenbusch
IPC分类号： H01L27108
CPC分类号： H01L23/5223 , H01L23/5222 , H01L23/66 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is configured as a high frequency-optimized capacitance and is distinguished by an extremely low sheet resistance, is connected in parallel with the MOS capacitances. By connecting the areally highly effective MOS capacitance, which, however, is connected with a somewhat higher impedance, in parallel with areally less effective metal capacitances, which, however, are connected to the supply voltage in a very low-impedance manner, it is possible to obtain broadband buffering and thus decoupling of high-frequency interference signals. Very high-frequency interference components are attenuated on the chip and do not pass into the system surrounding the integrated circuit.
摘要翻译：描述了具有用于平滑电源电压的电容元件的集成电路。在这种情况下，配置为高频优化电容并且被极低的薄层电阻区分的至少一个附加金属电极与MOS电容并联连接。然而，通过连接非常有效的MOS电容，该MOS电容与稍高阻抗连接，与以非常低阻抗的方式连接到电源电压的非常不太有效的金属电容并联。可能获得宽带缓冲，从而解耦高频干扰信号。非常高频的干扰元件在芯片上衰减，不会进入集成电路周围的系统。

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