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1. 发明授权

US06775736B2 Embedded DRAM system having wide data bandwidth and data transfer data protocol 有权
标题翻译：具有宽数据带宽和数据传输数据协议的嵌入式DRAM系统
公开(公告)号：US06775736B2
公开(公告)日：2004-08-10
申请号：US10062812
申请日：2002-01-31
申请人： Louis L. Hsu , Rajiv J. Joshi , Jeremy K. Stephens , Daniel W. Storaska
发明人： Louis L. Hsu , Rajiv J. Joshi , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G06F1200
CPC分类号： G11C7/1048 , G06F13/4243 , G11C5/063 , G11C11/4096 , G11C29/846 , G11C2207/104
摘要： A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.
摘要翻译：一种具有多个数据路径的宽数据宽度半导体存储器系统的自定时数据通信系统。数据通信系统包括被配置为存储数据的多个数据库，其中多个数据库中的相应数据库连接到多个数据路径中相应的一个数据路径。数据通信系统还包括用于根据接收到指示数据传送操作已被启动以用于将数据传送到相应的一个数据路径或从相应的一个数据路径传送数据的监视信号来控制相应的一个数据路径的电路。用于控制的电路包括用于产生控制信号的电路，该控制信号用于在传送数据以准备随后的数据传送操作之后控制相应的一个数据路径的复位。

2. 发明授权

US06614714B2 Semiconductor memory system having a data clock system for reliable high-speed data transfers 失效
标题翻译：具有用于可靠的高速数据传输的数据时钟系统的半导体存储器系统
公开(公告)号：US06614714B2
公开(公告)日：2003-09-02
申请号：US10055149
申请日：2002-01-22
申请人： Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska , Li-Kong Wang
发明人： Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska , Li-Kong Wang
IPC分类号： G11C818
CPC分类号： G11C7/222 , G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers. In the inventive system and method the clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.
摘要翻译：提供了一种用于半导体存储器系统的数据时钟系统，用于执行可靠的高速数据传输。半导体存储器系统包括被配置为存储数据的多个数据库，所述多个数据库与多个第一数据路径可操作地通信，每个第一数据路径与第二数据路径可操作地通信。数据时钟系统包括在数据传输操作期间接收时钟信号的第一时钟路径，用于经由多个第一数据路径中的一个数据路径在多个数据库的一个数据组和第二数据路径之间传送数据; 以及第二时钟路径，从第一时钟路径接收时钟信号并且沿着其传播时钟信号，第二时钟路径包括至少一个时钟驱动器。在所述至少一个时钟驱动器接收到所述时钟信号之后，发生所述多个第一数据路径中的一个数据路径和所述第二数据路径之间的数据传送。还提供了用于在半导体存储器系统中传播时钟信号的方法，用于执行可靠的高速数据传输。在本发明的系统和方法中，时钟信号在沿着第一时钟路径和第二时钟路径传播期间被延迟大约相同的时间量，而不管至少一个时钟驱动器位于第二时钟路径的远端附近，至少一个时钟驱动器位于第二时钟路径的近端附近。

3. 发明授权

US06449202B1 DRAM direct sensing scheme 失效
标题翻译： DRAM直接感测方案
公开(公告)号：US06449202B1
公开(公告)日：2002-09-10
申请号：US09929593
申请日：2001-08-14
申请人： Hiroyuki Akatsu , Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska
发明人： Hiroyuki Akatsu , Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G11C700
CPC分类号： G11C7/062 , G11C11/4091
摘要： A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line. When sensing a low data signal, the signal developed on the bitline causes subthreshold voltage leakage current through the pFET device to charge the gate of the nFET device which is floating to amplify the signal developed on the bitline to pull down the precharged data line. When sensing a high data signal, the pFET device and the nFET device remain inactivated, and the data line remains at its precharge high voltage. An nFET writeback device is coupled between the data line and the bitline which is switched on to begin a data writeback into the memory cell when the signal develops on the data line.
摘要翻译：一种直接感测电路和方法，用于在数据读取操作中在数据线上从连接到位线的存储器单元读取数据，并且将数据线开放位线检测而不使用参考位线信号。在数据读取操作之前，位线和数据线都被预充电到预充电电压，并且感测节点被预充电到地。 pFET器件的栅极耦合到从存储器单元在位线上产生的信号，以检测和放大其信号电平，并且其源极耦合到耦合到感测节点的电压源及其漏极，使得信号发展位线决定了pFET器件导通的程度。 nFET器件的栅极耦合到感测节点以检测和放大其信号电平，并且其漏极耦合到数据线。当感测到低数据信号时，在位线上产生的信号导致通过pFET器件的阈值电压漏电流，以对nFET器件的栅极进行充电，该nFET器件的栅极被浮置以放大在位线上产生的信号，以将预充电的数据线拉下来。当感测高数据信号时，pFET器件和nFET器件保持不激活，并且数据线保持在其预充电高电压。当在数据线上产生信号时，nFET写回装置耦合在数据线和打开的位线之间，以开始对存储器单元的数据写回。

4. 发明授权

US06552944B2 Single bitline direct sensing architecture for high speed memory device 有权
标题翻译：用于高速存储器件的单位线直接感测架构
公开(公告)号：US06552944B2
公开(公告)日：2003-04-22
申请号：US09870755
申请日：2001-05-31
申请人： John A. Fifield , Toshiaki Kirihata , Wing K. Luk , Jeremy K. Stephens , Daniel W. Storaska
发明人： John A. Fifield , Toshiaki Kirihata , Wing K. Luk , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G11C702
CPC分类号： G11C7/067 , G11C7/062 , G11C11/4091
摘要： A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ0, EQ1, are developed to allow for bitline shielding in the array.
摘要翻译：单个位线直接感测架构采用位于每个存储器阵列中的4晶体管读出放大器电路，其中晶体管用于选择性地将数据位从位线对的真位置或补码位线传送到数据线。数据线优选地布置在多个存储器阵列上。读取和写入操作可能共享或不共享数据行。一个电流源另外用于在读取模式下对数据进行预充电，通过检测电流源和由相应阵列的位线驱动的晶体管之间的电阻比来执行数字感测方案的功能。可以使用简单的逆变器来检测由电阻比确定的数据线的电平。以单端方式检测位线对，消除了对交叉耦合的CMOS器件的需要，从而减少了所需的布局面积。通过单独访问位线对，开发了用于预充电EQ0，EQ1的两组控制信号，以允许阵列中的位线屏蔽。

5. 发明授权

US07352815B2 Data transceiver and method for equalizing the data eye of a differential input data signal 有权
标题翻译：用于均衡差分输入数据信号的数据眼的数据收发器和方法
公开(公告)号：US07352815B2
公开(公告)日：2008-04-01
申请号：US10604025
申请日：2003-06-23
申请人： Hibourahima Camara , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Jeremy K. Stephens , Daniel W. Storaska
发明人： Hibourahima Camara , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： H04B3/00
CPC分类号： H04L25/03885
摘要： Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye of the differential input data signal is modified at the transmitter in response to feedback from the receiver where the extent of the data eye of the differential input data signal, after being conducted through the data link, is determined. The feedback to the transmitter, dependent on the determination of the extent of the data eye, controls the data eye at the transmitter and the equalization of the differential input data signal by adapting the differential input data signal to anticipate high frequency attenuation of the differential input data signal in the data link.
摘要翻译：当通过数据链路传送信号时，抵消差分输入数据信号的高频衰减的装置和方法。差分输入数据信号通过数据链路从发送器发送到接收器。差分输入数据信号的数据眼睛响应于来自接收机的反馈在发射机处被修改，其中差分输入数据信号在通过数据链路传导之后的数据眼的程度被确定。取决于数据眼的范围的确定，对发射机的反馈通过调整差分输入数据信号来预测差分输入的高频衰减来控制发射机上的数据眼和差分输入数据信号的均衡数据链路中的数据信号。

6. 发明授权

US06711078B2 Writeback and refresh circuitry for direct sensed DRAM macro 有权
标题翻译：用于直接感测DRAM宏的回写和刷新电路
公开(公告)号：US06711078B2
公开(公告)日：2004-03-23
申请号：US10064306
申请日：2002-07-01
申请人： Ciaran J. Brennan , John A. Fifield , Jeremy K. Stephens , Daniel W. Storaska
发明人： Ciaran J. Brennan , John A. Fifield , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： B11C700
CPC分类号： G11C11/40615 , G11C7/065 , G11C7/1051 , G11C7/1069 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.
摘要翻译：用于直接感测架构存储器的回写和刷新电路，其中多个主感测放大器连接到全局数据线，并且还连接到位线，每个位线被耦合到被选择用于写入和读取操作的存储器存储单元的阵列通过多个字线。单个次级感测放大器从全局数据线上的主感测放大器接收模拟电平数据，并且包括恢复/回写电路，其对数据进行数字化，然后将数字化数据通过全局数据线返回到主感测放大器并且返回记忆。每个存储器读取周期，第一周期读取操作和第二个周期回写操作都使用2周期读/写操作。 2周期的破坏性读取架构不需要缓存和复杂的缓存算法。

7. 发明授权

US07145413B2 Programmable impedance matching circuit and method 失效
标题翻译：可编程阻抗匹配电路及方法
公开(公告)号：US07145413B2
公开(公告)日：2006-12-05
申请号：US10250177
申请日：2003-06-10
申请人： Louis L. Hsu , Joseph Natonio , Daniel W. Storaska , William F. Washburn
发明人： Louis L. Hsu , Joseph Natonio , Daniel W. Storaska , William F. Washburn
IPC分类号： H03H7/38
CPC分类号： H03H7/38
摘要： As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.
摘要翻译：如本文所公开的，提供微电子电路和方法来改善传输线处的信号完整性。该电路包括可编程调节的阻抗匹配电路，其耦合到包括可编程调节的电感元件的传输线。可编程可调节阻抗匹配电路理想地设置在与传输线耦合的接收器或发射器相同的芯片上，或者替代地在与包括接收器或发射器的芯片一起封装的元件上。可编程可调阻抗匹配电路的阻抗可以响应于控制输入而调节，以改善传输线处的信号完整性。

8. 发明授权

US06751152B2 Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage 失效
标题翻译：方法和配置允许在增加具有存取晶体管阈值电压的感测信号的同时降低字线升压电压操作
公开(公告)号：US06751152B2
公开(公告)日：2004-06-15
申请号：US09999379
申请日：2001-10-31
申请人： Louis L. Hsu , Toshiaki K. Kirihata , Daniel W. Storaska
发明人： Louis L. Hsu , Toshiaki K. Kirihata , Daniel W. Storaska
IPC分类号： G11C800
CPC分类号： G11C11/4085 , G11C7/065 , G11C11/4091
摘要： A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used. Lowering the wordline voltage results in a reduction in power consumption by saving power on Vpp generator and support circuits, and a reduction in the size of the Vpp generator and support circuits, and also eliminates high Vpp voltage related problems such as dielectric breakdown and other reliability concerns while avoiding a complex decoding scheme and saving cost.
摘要翻译：存储器阵列架构采用全Vdd位线预充电电压和低字线升压电压，其小于Vdd加上存取晶体管的阈值电压。在写入模式中，数据位的第一低电平几乎完全写入存储元件，然而数据位的第二高电平未完全写入存储元件。在读取模式下，数据位的第一低电平从存储元件完全读出，然而数据位的第二高电平不通过利用存取晶体管阈值电压被读出。这允许感测信号仅在第一电压电平传输到Vdd预充电BL。参考WL优选地用于产生用于差分Vdd感测方案的参考位线电压。或者，可以使用单个BL数字感测方案。降低字线电压通过节省Vpp发生器和支持电路上的功率以及减小Vpp发生器和支持电路的尺寸而降低功耗，并且消除了与Vpp电压相关的高电压问题，例如介质击穿和其他可靠性同时避免复杂的解码方案并节省成本。

9. 发明授权

US07265433B2 On-pad broadband matching network 失效
标题翻译：在线宽带匹配网络
公开(公告)号：US07265433B2
公开(公告)日：2007-09-04
申请号：US10905624
申请日：2005-01-13
申请人： Edward R. Pillai , Louis L. Hsu , Wolfgang Sauter , Daniel W. Storaska
发明人： Edward R. Pillai , Louis L. Hsu , Wolfgang Sauter , Daniel W. Storaska
IPC分类号： H02H3/22
CPC分类号： H01L23/5227 , H01L23/66 , H01L24/05 , H01L24/48 , H01L27/0255 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05556 , H01L2224/05599 , H01L2224/131 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00011 , H01L2224/45099 , H01L2924/00
摘要： A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.
摘要翻译：提供了芯片，其中片上匹配网络具有导电连接到芯片的焊盘的第一端子和导电连接到芯片上的公共节点的第二端子。接线迹线将片上匹配网络连接到芯片的电路。片上匹配网络包括具有至少一个二极管的静电放电保护（ESD）电路，其具有导电连接到接合焊盘的第一端子和连接到固定电位源的过电压放电路径的第二端子。匹配网络还包括耦合以在接合焊盘和布线迹线之间提供第一感应路径的第一电感器，具有连接到公共节点的第一端子的终端电阻器，以及耦合以在第二电感器之间提供第二电感路径的第二电感器接线迹线和终端电阻的第二个端子。

10. 发明授权

US08040813B2 Apparatus and method for reduced loading of signal transmission elements 有权
标题翻译：信号传输元件负载减小的装置和方法
公开(公告)号：US08040813B2
公开(公告)日：2011-10-18
申请号：US10908959
申请日：2005-06-02
申请人： Louis L. Hsu , Karl D. Selander , Michael A. Sorna , Daniel W. Storaska
发明人： Louis L. Hsu , Karl D. Selander , Michael A. Sorna , Daniel W. Storaska
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H03K17/16 , G05F1/00 , H03K5/01 , H03K9/00 , H03K5/00 , H03K19/0175 , G01N30/86
CPC分类号： G06F13/4072
摘要： An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.
摘要翻译：提供一种装置，其包括可操作以传导第一信号的公共信号节点，耦合到公共信号节点以利用第一信号的第一电路和耦合到公共信号节点的信号处理元件。信号处理元件包括耦合到第一导体的隔离电路，可操作以导通隔离电路的输出的第二导体和耦合到第二导体的信号处理电路。信号处理电路可操作以响应于隔离电路的输出执行信号处理功能。通过隔离电路，信号处理电路和第一电路与第二导体和信号处理电路隔离。优选地，所实现的隔离允许包含在第一信号中的通信信号在具有较小电容的通信设备内传导，并且产生较小的该信号的回波损耗。

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