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1. 发明申请

US20070252613A1 UNIVERSAL CMOS DEVICE LEAKAGE CHARACTERIZATION SYSTEM 有权
标题翻译：通用CMOS器件泄漏特性系统
公开(公告)号：US20070252613A1
公开(公告)日：2007-11-01
申请号：US11380515
申请日：2006-04-27
申请人： Louis Hsu , Edward Pillai , Joseph Natonio , James Rockrohr , David Hanson
发明人： Louis Hsu , Edward Pillai , Joseph Natonio , James Rockrohr , David Hanson
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/3008 , G01R31/318577
摘要： The invention provides a universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.
摘要翻译：本发明提供了一种通用泄漏监测系统（ULMS），用于在开发制造过程或正常操作期期间测量多个泄漏宏。 ULMS表征了栅极电介质泄漏，亚阈值泄漏和反向偏置结漏电以及n型和p型CMOS器件的泄漏等。使用片上算法从第一测试宏到最后一个测试宏顺序执行测试。当测试最后一个测试宏时，会扫描泄漏数据。

2. 发明授权

US07486114B2 Signal detector with calibration circuit arrangement 有权
标题翻译：具有校准电路布置的信号检测器
公开(公告)号：US07486114B2
公开(公告)日：2009-02-03
申请号：US11383821
申请日：2006-05-17
申请人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： H03K5/19
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.
摘要翻译：一种用于检测输入差分信号的存在或不存在的信号检测器和方法。该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

3. 发明申请

US20070271054A1 Signal Detector with Calibration Circuit Arrangement 有权
标题翻译：具有校准电路布置的信号检测器
公开(公告)号：US20070271054A1
公开(公告)日：2007-11-22
申请号：US11383821
申请日：2006-05-17
申请人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： G06F19/00
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A signal detector and method detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.
摘要翻译：信号检测器和方法检测输入差分信号的存在或不存在。该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

4. 发明授权

US06949981B2 Dynamic threshold for VCO calibration 有权
标题翻译： VCO校准的动态阈值
公开(公告)号：US06949981B2
公开(公告)日：2005-09-27
申请号：US10708233
申请日：2004-02-18
申请人： Joseph Natonio , Michael A. Sorna
发明人： Joseph Natonio , Michael A. Sorna
IPC分类号： H03L7/00 , H03L7/099 , H03L7/10 , H03L7/18
CPC分类号： H03L7/099 , H03L7/10 , H03L7/18
摘要： A voltage controlled oscillator (VCO) is provided which includes a threshold level setting circuit operable to set a lower variable threshold level and to set an upper variable threshold level. The VCO includes a frequency band selection unit operable to adjust a frequency band setting of the VCO to one of a plurality of frequency band settings. The VCO further includes a comparator operable to determine whether a control voltage of the VCO falls between the lower threshold level and the upper threshold level. The VCO further includes a threshold adjustment and calibration circuit operable to maintain the frequency band setting when the control voltage falls between the lower and upper threshold levels. Otherwise, when the control voltage lies below the lower threshold level, the lower threshold level is adjusted downward and the upper threshold level is adjusted upward, and when the control voltage lies above the upper threshold level, the frequency band selection is increased to a next higher frequency band.
摘要翻译：提供了一种压控振荡器（VCO），其包括阈值电平设置电路，其可操作以设置较低的可变阈值电平并设置较高的可变阈值电平。 VCO包括频带选择单元，其可操作以将VCO的频带设置调整为多个频带设置中的一个。 VCO还包括比较器，其可操作以确定VCO的控制电压是否落在下阈值电平和上阈值电平之间。 VCO还包括阈值调整和校准电路，其可操作以在控制电压落在下限和上限阈值水平之间时维持频带设置。否则，当控制电压低于下阈值电平时，下阈值电平向下调整，上阈值电平向上调整，当控制电压高于上阈值电平时，频段选择增加到下一阈值较高频段。

5. 发明申请

US20050179501A1 DYNAMIC THRESHOLD FOR VCO CALIBRATION 有权
标题翻译：用于VCO校准的动态阈值
公开(公告)号：US20050179501A1
公开(公告)日：2005-08-18
申请号：US10708233
申请日：2004-02-18
申请人： Joseph Natonio , Michael Sorna
发明人： Joseph Natonio , Michael Sorna
IPC分类号： H03L7/00 , H03L7/099 , H03L7/10 , H03L7/18
CPC分类号： H03L7/099 , H03L7/10 , H03L7/18
摘要： A voltage controlled oscillator (VCO) is provided which includes a threshold level setting circuit operable to set a lower variable threshold level and to set an upper variable threshold level. The VCO includes a frequency band selection unit operable to adjust a frequency band setting of the VCO to one of a plurality of frequency band settings. The VCO further includes a comparator operable to determine whether a control voltage of the VCO falls between the lower threshold level and the upper threshold level. The VCO further includes a threshold adjustment and calibration circuit operable to maintain the frequency band setting when the control voltage falls between the lower and upper threshold levels. Otherwise, when the control voltage lies below the lower threshold level, the lower threshold level is adjusted downward and the upper threshold level is adjusted upward, and when the control voltage lies above the upper threshold level, the frequency band selection is increased to a next higher frequency band.
摘要翻译：提供了一种压控振荡器（VCO），其包括阈值电平设置电路，其可操作以设置较低的可变阈值电平并设置较高的可变阈值电平。 VCO包括频带选择单元，其可操作以将VCO的频带设置调整为多个频带设置中的一个。 VCO还包括比较器，其可操作以确定VCO的控制电压是否落在下阈值电平和上阈值电平之间。 VCO还包括阈值调整和校准电路，其可操作以在控制电压落在下限和上限阈值水平之间时维持频带设置。否则，当控制电压低于下阈值电平时，下阈值电平向下调整，上阈值电平向上调整，当控制电压高于上阈值电平时，频段选择增加到下一阈值较高频段。

6. 发明授权

US08219041B2 Design structure for transmitter bandwidth optimization circuit 有权
标题翻译：发射机带宽优化电路的设计结构
公开(公告)号：US08219041B2
公开(公告)日：2012-07-10
申请号：US11985963
申请日：2007-11-19
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
IPC分类号： H04B1/02
CPC分类号： H04L25/0286 , H04L25/03343
摘要： A design structure embodied in a machine-readable medium used in a design process provides a transmitter having a frequency response controllable in accordance with an operational parameter, and may include a storage operable to store operational parameters for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. A sensor can be used to detect an operating condition. In response to a change in the detected operating condition, a stored operational parameter corresponding to the detected operating condition can be used to control the frequency response of the transmitter.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构提供具有根据操作参数可控的频率响应的发射机，并且可以包括可操作地存储用于控制每个发射机的频率响应的操作参数的存储器的多个相应的操作条件。可以使用传感器来检测操作状态。响应于检测到的操作条件的变化，可以使用与检测到的操作条件对应的存储的操作参数来控制发送器的频率响应。

7. 发明申请

US20090108885A1 Design structure for CMOS differential rail-to-rail latch circuits 审中-公开
标题翻译： CMOS差分轨到轨锁存电路的设计结构
公开(公告)号：US20090108885A1
公开(公告)日：2009-04-30
申请号：US11982206
申请日：2007-10-31
申请人： Joseph Natonio , Steven J. Zier
发明人： Joseph Natonio , Steven J. Zier
IPC分类号： H03K3/3562 , H03K21/00 , H03K3/00
CPC分类号： H03K3/35625
摘要： A design structure including a CMOS rail-to-rail differential latch is provided in which a plurality of cross-coupled devices pull first and second nodes of the latch to opposite rail-to-rail voltages. Desirably, first and second output isolating elements have inputs coupled to the first and second nodes, the output isolating elements being operable to output versions of the opposite rail-to-rail voltages as a true and a complementary output of the latch. In this way, the true output has a rising edge occurring simultaneously with a falling edge of the complementary output. The complementary output has a rising edge occurring simultaneously with a falling edge of the true output. First and second input isolating elements of the latch have outputs coupled to the first and second nodes, the first and second input isolating elements being operable to apply versions of input signals to the first and second nodes.
摘要翻译：提供了包括CMOS轨到轨差分锁存器的设计结构，其中多个交叉耦合器件将闩锁的第一和第二节点拉到相对的轨至轨电压。期望地，第一和第二输出隔离元件具有耦合到第一和第二节点的输入，输出隔离元件可操作以将相对的轨至轨电压的版本输出为锁存器的真实和互补输出。以这种方式，真正的输出具有与互补输出的下降沿同时出现的上升沿。互补输出具有与真实输出的下降沿同时发生的上升沿。锁存器的第一和第二输入隔离元件具有耦合到第一和第二节点的输出，第一和第二输入隔离元件可操作以将输入信号的版本应用于第一和第二节点。

8. 发明申请

US20080129329A1 Method of testing connectivity using dual operational mode CML latch 失效
标题翻译：使用双操作模式CML锁定测试连接的方法
公开(公告)号：US20080129329A1
公开(公告)日：2008-06-05
申请号：US12002878
申请日：2007-12-19
申请人： Joseph O. Marsh , Joseph Natonio , James M. Wilson
发明人： Joseph O. Marsh , Joseph Natonio , James M. Wilson
IPC分类号： H03K19/003
CPC分类号： H03K3/356043
摘要： A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at least one clock signal and having a mode control device for operating the CML latch circuit as a buffer amplifier when the at least one clock signal is inactive. The method comprises the steps of activating the mode control devices of each of the CML latches to operate each of the CML latches as a buffer; inputting a first signal to a first CML latch of the series; latching an output signal of a second CML latch of the series, the second CML latch being connected at a point in the series downstream from the first CML latch; and determining whether the output signal changes in accordance with a change in the first signal.
摘要翻译：提供了通过串联连接的多个双用途电流模式逻辑（“CML”）锁存电路来测试连接性的方法。每个CML锁存电路可操作以根据至少一个时钟信号在定时锁存至少一个输出信号，并具有一个模式控制装置，用于当至少一个时钟信号为不活跃该方法包括以下步骤：激活每个CML锁存器的模式控制装置，以操作每个CML锁存器作为缓冲器; 向所述系列的第一CML锁存器输入第一信号; 锁存串联的第二CML锁存器的输出信号，第二CML锁存器在第一CML锁存器下游的串联点连接; 以及确定所述输出信号是否根据所述第一信号的改变而改变。

9. 发明授权

US06584606B1 Fast method of I/O circuit placement and electrical rule checking 失效
标题翻译：快速的I / O电路放置方法和电气规则检查
公开(公告)号：US06584606B1
公开(公告)日：2003-06-24
申请号：US09584416
申请日：2000-06-01
申请人： Charles S. Chiu , James P. Libous , Rory D. Loughran , Joseph Natonio , Robert A. Proctor , Gulsun Yasar
发明人： Charles S. Chiu , James P. Libous , Rory D. Loughran , Joseph Natonio , Robert A. Proctor , Gulsun Yasar
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.
摘要翻译：分析集成电路（例如ASIC）的I / O单元布局的方法包括在所选择的芯片图像上定义所提出的I / O单元布局，为电迁移，IR电压降和di / dt噪声提供一组限制规则所选择的芯片图像，为所提出的I / O单元布局中使用的每个I / O单元类型提供特征，通过对所提出的I / O单元布局应用限制规则来检查所提出的I / O单元布局，并报告所有I / 在所提出的I / O单元布局中使用的O单元不符合所选芯片图像的限制规则。

10. 发明授权

US06499134B1 Method of assigning integrated circuit I/O signals in an integrated circuit package 有权
标题翻译：在集成电路封装中分配集成电路I / O信号的方法
公开(公告)号：US06499134B1
公开(公告)日：2002-12-24
申请号：US09615149
申请日：2000-07-13
申请人： Patrick H. Buffet , Paul E. Dunn , Joseph Natonio , Robert A. Proctor , Gulsun Yasar
发明人： Patrick H. Buffet , Paul E. Dunn , Joseph Natonio , Robert A. Proctor , Gulsun Yasar
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for improving the crosstalk and time-of-flight performance for signals in an integrated circuit with respect to the package-related wiring. I/O pads in the package-related wiring of a logic design meeting specified crosstalk and time-of-flight constraints are identified using a software tool. The tool produces a graphical display in which the identified I/O pads are highlighted. The tool enables a user to graphically manipulate the display to assign, i.e., establish an electrical connection, between I/O circuits corresponding to the signals and the highlighted I/O pads.
摘要翻译：一种用于改善集成电路中针对封装相关布线的信号的串扰和飞行时间性能的方法。使用软件工具识别逻辑设计会议规定的串扰和飞行时间限制的封装相关布线中的I / O焊盘。该工具产生图形显示，其中识别的I / O焊盘被突出显示。该工具使得用户能够以图形方式操纵显示器，以分配对应于信号的I / O电路和突出显示的I / O焊盘之间的电连接。

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