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    • 5. 发明申请
    • Design structure for CMOS differential rail-to-rail latch circuits
    • CMOS差分轨到轨锁存电路的设计结构
    • US20090108885A1
    • 2009-04-30
    • US11982206
    • 2007-10-31
    • Joseph NatonioSteven J. Zier
    • Joseph NatonioSteven J. Zier
    • H03K3/3562H03K21/00H03K3/00
    • H03K3/35625
    • A design structure including a CMOS rail-to-rail differential latch is provided in which a plurality of cross-coupled devices pull first and second nodes of the latch to opposite rail-to-rail voltages. Desirably, first and second output isolating elements have inputs coupled to the first and second nodes, the output isolating elements being operable to output versions of the opposite rail-to-rail voltages as a true and a complementary output of the latch. In this way, the true output has a rising edge occurring simultaneously with a falling edge of the complementary output. The complementary output has a rising edge occurring simultaneously with a falling edge of the true output. First and second input isolating elements of the latch have outputs coupled to the first and second nodes, the first and second input isolating elements being operable to apply versions of input signals to the first and second nodes.
    • 提供了包括CMOS轨到轨差分锁存器的设计结构,其中多个交叉耦合器件将闩锁的第一和第二节点拉到相对的轨至轨电压。 期望地,第一和第二输出隔离元件具有耦合到第一和第二节点的输入,输出隔离元件可操作以将相对的轨至轨电压的版本输出为锁存器的真实和互补输出。 以这种方式,真正的输出具有与互补输出的下降沿同时出现的上升沿。 互补输出具有与真实输出的下降沿同时发生的上升沿。 锁存器的第一和第二输入隔离元件具有耦合到第一和第二节点的输出,第一和第二输入隔离元件可操作以将输入信号的版本应用于第一和第二节点。
    • 8. 发明申请
    • CMOS DIFFERENTIAL RAIL-TO-RAIL LATCH CIRCUITS
    • CMOS差分轨至轨电路
    • US20080180139A1
    • 2008-07-31
    • US11668137
    • 2007-01-29
    • Joseph NatonioSteven J. Zier
    • Joseph NatonioSteven J. Zier
    • H03K3/356H03B19/00
    • H03K3/356121H03K3/35625
    • A CMOS rail-to-rail differential latch is provided in which a plurality of cross-coupled devices pull first and second nodes of the latch to opposite rail-to-rail voltages. Desirably, first and second output isolating elements have inputs coupled to the first and second nodes, the output isolating elements being operable to output versions of the opposite rail-to-rail voltages as a true and a complementary output of the latch. In this way, the true output has a rising edge occurring simultaneously with a falling edge of the complementary output. The complementary output has a rising edge occurring simultaneously with a falling edge of the true output. First and second input isolating elements of the latch have outputs coupled to the first and second nodes, the first and second input isolating elements being operable to apply versions of input signals to the first and second nodes.
    • 提供了CMOS轨对轨差分锁存器,其中多个交叉耦合器件将锁存器的第一和第二节点拉到相对的轨到轨电压。 期望地,第一和第二输出隔离元件具有耦合到第一和第二节点的输入,输出隔离元件可操作以将相对的轨至轨电压的版本输出为锁存器的真实和互补输出。 以这种方式,真正的输出具有与互补输出的下降沿同时出现的上升沿。 互补输出具有与真实输出的下降沿同时发生的上升沿。 锁存器的第一和第二输入隔离元件具有耦合到第一和第二节点的输出,第一和第二输入隔离元件可操作以将输入信号的版本应用于第一和第二节点。
    • 9. 发明授权
    • Dynamic threshold for VCO calibration
    • VCO校准的动态阈值
    • US06949981B2
    • 2005-09-27
    • US10708233
    • 2004-02-18
    • Joseph NatonioMichael A. Sorna
    • Joseph NatonioMichael A. Sorna
    • H03L7/00H03L7/099H03L7/10H03L7/18
    • H03L7/099H03L7/10H03L7/18
    • A voltage controlled oscillator (VCO) is provided which includes a threshold level setting circuit operable to set a lower variable threshold level and to set an upper variable threshold level. The VCO includes a frequency band selection unit operable to adjust a frequency band setting of the VCO to one of a plurality of frequency band settings. The VCO further includes a comparator operable to determine whether a control voltage of the VCO falls between the lower threshold level and the upper threshold level. The VCO further includes a threshold adjustment and calibration circuit operable to maintain the frequency band setting when the control voltage falls between the lower and upper threshold levels. Otherwise, when the control voltage lies below the lower threshold level, the lower threshold level is adjusted downward and the upper threshold level is adjusted upward, and when the control voltage lies above the upper threshold level, the frequency band selection is increased to a next higher frequency band.
    • 提供了一种压控振荡器(VCO),其包括阈值电平设置电路,其可操作以设置较低的可变阈值电平并设置较高的可变阈值电平。 VCO包括频带选择单元,其可操作以将VCO的频带设置调整为多个频带设置中的一个。 VCO还包括比较器,其可操作以确定VCO的控制电压是否落在下阈值电平和上阈值电平之间。 VCO还包括阈值调整和校准电路,其可操作以在控制电压落在下限和上限阈值水平之间时维持频带设置。 否则,当控制电压低于下阈值电平时,下阈值电平向下调整,上阈值电平向上调整,当控制电压高于上阈值电平时,频段选择增加到下一阈值 较高频段。
    • 10. 发明申请
    • DYNAMIC THRESHOLD FOR VCO CALIBRATION
    • 用于VCO校准的动态阈值
    • US20050179501A1
    • 2005-08-18
    • US10708233
    • 2004-02-18
    • Joseph NatonioMichael Sorna
    • Joseph NatonioMichael Sorna
    • H03L7/00H03L7/099H03L7/10H03L7/18
    • H03L7/099H03L7/10H03L7/18
    • A voltage controlled oscillator (VCO) is provided which includes a threshold level setting circuit operable to set a lower variable threshold level and to set an upper variable threshold level. The VCO includes a frequency band selection unit operable to adjust a frequency band setting of the VCO to one of a plurality of frequency band settings. The VCO further includes a comparator operable to determine whether a control voltage of the VCO falls between the lower threshold level and the upper threshold level. The VCO further includes a threshold adjustment and calibration circuit operable to maintain the frequency band setting when the control voltage falls between the lower and upper threshold levels. Otherwise, when the control voltage lies below the lower threshold level, the lower threshold level is adjusted downward and the upper threshold level is adjusted upward, and when the control voltage lies above the upper threshold level, the frequency band selection is increased to a next higher frequency band.
    • 提供了一种压控振荡器(VCO),其包括阈值电平设置电路,其可操作以设置较低的可变阈值电平并设置较高的可变阈值电平。 VCO包括频带选择单元,其可操作以将VCO的频带设置调整为多个频带设置中的一个。 VCO还包括比较器,其可操作以确定VCO的控制电压是否落在下阈值电平和上阈值电平之间。 VCO还包括阈值调整和校准电路,其可操作以在控制电压落在下限和上限阈值水平之间时维持频带设置。 否则,当控制电压低于下阈值电平时,下阈值电平向下调整,上阈值电平向上调整,当控制电压高于上阈值电平时,频段选择增加到下一阈值 较高频段。