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    • 1. 发明授权
    • Controlling memory access devices in a data driven architecture mesh array
    • 控制数据驱动架构网格数组中的内存访问设备
    • US07827386B2
    • 2010-11-02
    • US10611377
    • 2003-06-30
    • Louis A. LippincottChin Hong Cheah
    • Louis A. LippincottChin Hong Cheah
    • G06F15/00G06F15/76
    • G06F9/4494
    • A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading from or writing to external memory, sets up a logical channel between a second processing unit of the processor and the external memory, to transfer additional data between the external memory and the second processing unit. This capability may be implemented by the addition of a control port, separate from data ports, to the first processing unit, where the control port allows the first processing unit to write addressing information and mode information (including the location of the additional data) for reading or writing the additional data via a memory access unit data channel of the processor.
    • 将第一组指令和输入数据提供给数据驱动处理器的第一处理单元,以对输入的数据进行操作。 第一处理单元响应于识别第一组指令需要从外部存储器读取或写入外部存储器,在处理器的第二处理单元和外部存储器之间建立逻辑通道,以在第二处理单元之间传送附加数据 外部存储器和第二处理单元。 该能力可以通过添加与数据端口分离的控制端口到第一处理单元来实现,其中控制端口允许第一处理单元将寻址信息和模式信息(包括附加数据的位置)写入 通过处理器的存储器访问单元数据通道读取或写入附加数据。
    • 2. 发明授权
    • Internet domain and time index based video email system
    • 基于互联网域和时间索引的视频电子邮件系统
    • US07020891B1
    • 2006-03-28
    • US09672372
    • 2000-09-28
    • Louis A. Lippincott
    • Louis A. Lippincott
    • H04N7/173
    • H04N7/17318H04N21/2347H04N21/26606H04N21/26613H04N21/4405H04N21/4623H04N21/4661H04N21/4667H04N21/47202H04N21/6587H04N21/835
    • A device is provided that includes a first processor connected to a communications channel device. The communications device is capable of receiving and transmitting information to a video-on-demand (VOD) service provider. A VOD content decoder is provided that is conencted to the first processor. A video and audio formatting processor is provided that is connected to the first processor and the content decoder. An index memory is provided that is connected to the first processor. The index memory stores a plurality of VOD program segment representations of either whole VOD program content or partial VOD program content. Also provided is a method that includes selecting a start and stop time for recording a representation of a segment of at least one VOD program. The method also includes converting a VOD program identifier of at least one VOD program to a text representation. Also, either converting the text representation of the VOD program identifier of at least one VOD program into a unique encoded digital representation or receiving a unique encoded digital representation from the VOD service provider. Converting the start and stop time for a segment of at least one VOD program to a digital representation. And storing the VOD program identifier encoded digital representation and the start and stop digital representation in an index memory.
    • 提供了一种包括连接到通信信道设备的第一处理器的设备。 通信设备能够接收和发送信息到视频点播(VOD)服务提供商。 提供一种与第一处理器相连的VOD内容解码器。 提供了连接到第一处理器和内容解码器的视频和音频格式化处理器。 提供了连接到第一处理器的索引存储器。 索引存储器存储整个VOD节目内容或部分VOD节目内容的多个VOD节目片段表示。 还提供了一种方法,其包括选择用于记录至少一个VOD节目的片段的表示的开始和停止时间。 该方法还包括将至少一个VOD节目的VOD节目标识符转换为文本表示。 此外,将至少一个VOD节目的VOD节目标识符的文本表示转换为唯一的编码数字表示,或者从VOD服务提供商接收唯一的编码数字表示。 将至少一个VOD程序的段的开始和停止时间转换为数字表示。 并将VOD节目标识符编码的数字表示和起始和停止数字表示存储在索引存储器中。
    • 3. 发明授权
    • Memory subsystem employing pool of refresh candidates
    • 内存子系统使用刷新候选库
    • US06366516B1
    • 2002-04-02
    • US09753005
    • 2000-12-29
    • Louis A. Lippincott
    • Louis A. Lippincott
    • G11C700
    • G11C11/406
    • A memory subsystem that includes a dynamic random-access memory (DRAM) having cells organized as an array of rows and columns, the cells being individually accessed by specifying a row address and a column address. An additional cell that stores a charge level is associated with each row of the DRAM. The charge level is characteristic of the charge level of the associated DRAM row, and is refreshed by a secondary or primary refresh cycle to the associated DRAM row. A threshold detector outputs a refresh signal when the charge of the additional cell drops below a predetermined threshold. Circuitry responsive to the refresh signal collects the row address of the additional cell and sends it to logic that generates a primary refresh cycle to the associated row address of the DRAM.
    • 一种包括动态随机存取存储器(DRAM)的存储器子系统,其具有被组织成行和列的阵列的单元,通过指定行地址和列地址来单独访问单元。 存储电荷电平的附加单元与DRAM的每一行相关联。 充电电平是相关DRAM行的充电电平的特征,并且被辅助或主刷新周期刷新到相关的DRAM行。 当附加单元的电荷下降到预定阈值以下时,阈值检测器输出刷新信号。 响应于刷新信号的电路收集附加单元的行地址,并将其发送到生成主要刷新周期的逻辑到DRAM的相关行地址。
    • 4. 发明授权
    • Method and apparatus for translating addresses using mask and
replacement value registers and for accessing a service routine in
response to a page fault
    • 用于使用掩码和替换值寄存器翻译地址以及响应于页面错误来访问服务例程的方法和装置
    • US5649142A
    • 1997-07-15
    • US476061
    • 1995-06-07
    • Gary LavelleLouis A. LippincottKevin HarneyDinesh G. Rao
    • Gary LavelleLouis A. LippincottKevin HarneyDinesh G. Rao
    • G06F9/30G06F9/38G06F12/10G06F13/00
    • G06F12/1081G06F9/30072G06F9/30149G06F9/3816G06F9/3863G06F9/3885G06F9/3887
    • A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and for accessing a service routine in response to a page fault, are described. In one embodiment, the apparatus for translating comprises a processor; a page table having a translation mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive values in the comparison value register until a match comparison value is found. If a match comparison value is found, a programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress to provide the second address. If a match comparison value is not found, a fault interrupt is generated to interrupt the translation and the processor accesses a service routine in accordance with the fault interrupt.
    • 一种用于将诸如处理器地址空间的第一地址空间中的第一地址转换到诸如系统地址空间的第二地址空间中的第二地址并且响应于页错误而访问服务例程的方法和装置 ,被描述。 在一个实施例中,用于翻译的装置包括处理器; 具有翻译屏蔽寄存器,比较值寄存器和替换值寄存器的页表; 以及耦合到比较值寄存器和替换值寄存器的比较器。 使用翻译掩码寄存器内的可编程掩码来分割虚拟地址。 第一子地址包括第一地址的比特的子集,第二子地址包括第一地址的剩余比特。 第一个子地址在转换掩码寄存器中用可编程掩码值进行掩码,并通过比较器与比较值寄存器中的连续值进行比较,直到找到匹配比较值。 如果找到匹配比较值,则与匹配比较值相对应的替换值寄存器中的可编程替换值与第二子地址相连接以提供第二地址。 如果未找到匹配比较值,则产生故障中断以中断转换,并且处理器根据故障中断访问服务程序。
    • 6. 发明授权
    • Improved system of resolving conflicting data processing memory access
requests
    • 改进的解决冲突数据处理存储器访问请求的系统
    • US5339442A
    • 1994-08-16
    • US954743
    • 1992-09-30
    • Louis A. Lippincott
    • Louis A. Lippincott
    • G06F13/18G06F13/362G06F13/364
    • G06F13/362G06F13/18
    • A request arbitration device is provided for prioritizing requests in a data processing system. A series of requests may arrive at the arbitration device at differing arrival times. The requests are accumulated to form a set of requests which is applied to a priority decode without any information on their relative arrival times. The priority device applies a fixed predetermined priority scheme to these requests. Simultaneously with the prioritizing of the first set of requests by the priority decode, a second set of requests may arrive at different arrival times. The requests of this second set of requests are likewise accumulated by the arbitration logic of a present invention. When arbitration of the first set of requests is complete, the second set of requests is then applied to the priority decode, again without any information with respect to their relative arrival times. The second set of requests is prioritized according to the same fixed predetermined priority scheme as the first set.
    • 提供请求仲裁装置用于在数据处理系统中优先处理请求。 一系列请求可能在不同到达时间到达仲裁设备。 这些请求被积累以形成一组请求,该请求被应用于优先解码,而没有关于其相对到达时间的任何信息。 优先级设备对这些请求应用固定的预定优先级方案。 与通过优先解码对第一组请求进行优先排列同时,第二组请求可以到达不同的到达时间。 第二组请求的请求同样地由本发明的仲裁逻辑积累。 当第一组请求的仲裁完成时,第二组请求然后再次应用于优先级解码,而没有关于它们的相对到达时间的任何信息。 第二组请求根据与第一组相同的固定预定优先级方案进行优先排序。
    • 7. 发明授权
    • Scalable multimedia platform architecture
    • 可扩展的多媒体平台架构
    • US5335321A
    • 1994-08-02
    • US901383
    • 1992-06-19
    • Kevin HarneyLouis A. Lippincott
    • Kevin HarneyLouis A. Lippincott
    • G06F3/14G06F13/42G06T11/00G09G5/36G06F15/20
    • G09G5/363G06F13/423G06F3/14
    • The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.
    • 本发明的视频处理系统发明的可扩展平台架构包括用于在各种视频处理子系统之间传输数据的总线。 图形处理子系统耦合到总线。 中央处理单元耦合到总线并执行视频处理。 图形处理子系统适于接收视频存储器并且在接收到视频存储器时执行视频处理。 总线上设置有用于可拆卸地耦合到视频处理子系统和视频捕获系统的扩展连接器。 视频处理子系统和/或视频捕获子系统的添加通过执行由中央处理单元执行的视频处理来加速视频处理系统的处理。