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1. 发明授权

US5649142A Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault 失效
标题翻译：用于使用掩码和替换值寄存器翻译地址以及响应于页面错误来访问服务例程的方法和装置
公开(公告)号：US5649142A
公开(公告)日：1997-07-15
申请号：US476061
申请日：1995-06-07
申请人： Gary Lavelle , Louis A. Lippincott , Kevin Harney , Dinesh G. Rao
发明人： Gary Lavelle , Louis A. Lippincott , Kevin Harney , Dinesh G. Rao
IPC分类号： G06F9/30 , G06F9/38 , G06F12/10 , G06F13/00
CPC分类号： G06F12/1081 , G06F9/30072 , G06F9/30149 , G06F9/3816 , G06F9/3863 , G06F9/3885 , G06F9/3887
摘要： A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and for accessing a service routine in response to a page fault, are described. In one embodiment, the apparatus for translating comprises a processor; a page table having a translation mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive values in the comparison value register until a match comparison value is found. If a match comparison value is found, a programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress to provide the second address. If a match comparison value is not found, a fault interrupt is generated to interrupt the translation and the processor accesses a service routine in accordance with the fault interrupt.
摘要翻译：一种用于将诸如处理器地址空间的第一地址空间中的第一地址转换到诸如系统地址空间的第二地址空间中的第二地址并且响应于页错误而访问服务例程的方法和装置，被描述。在一个实施例中，用于翻译的装置包括处理器; 具有翻译屏蔽寄存器，比较值寄存器和替换值寄存器的页表; 以及耦合到比较值寄存器和替换值寄存器的比较器。使用翻译掩码寄存器内的可编程掩码来分割虚拟地址。第一子地址包括第一地址的比特的子集，第二子地址包括第一地址的剩余比特。第一个子地址在转换掩码寄存器中用可编程掩码值进行掩码，并通过比较器与比较值寄存器中的连续值进行比较，直到找到匹配比较值。如果找到匹配比较值，则与匹配比较值相对应的替换值寄存器中的可编程替换值与第二子地址相连接以提供第二地址。如果未找到匹配比较值，则产生故障中断以中断转换，并且处理器根据故障中断访问服务程序。

2. 发明授权

US5335321A Scalable multimedia platform architecture 失效
标题翻译：可扩展的多媒体平台架构
公开(公告)号：US5335321A
公开(公告)日：1994-08-02
申请号：US901383
申请日：1992-06-19
申请人： Kevin Harney , Louis A. Lippincott
发明人： Kevin Harney , Louis A. Lippincott
IPC分类号： G06F3/14 , G06F13/42 , G06T11/00 , G09G5/36 , G06F15/20
CPC分类号： G09G5/363 , G06F13/423 , G06F3/14
摘要： The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.
摘要翻译：本发明的视频处理系统发明的可扩展平台架构包括用于在各种视频处理子系统之间传输数据的总线。图形处理子系统耦合到总线。中央处理单元耦合到总线并执行视频处理。图形处理子系统适于接收视频存储器并且在接收到视频存储器时执行视频处理。总线上设置有用于可拆卸地耦合到视频处理子系统和视频捕获系统的扩展连接器。视频处理子系统和/或视频捕获子系统的添加通过执行由中央处理单元执行的视频处理来加速视频处理系统的处理。

3. 发明授权

US5640528A Method and apparatus for translating addresses using mask and replacement value registers 失效
标题翻译：使用掩码和替换值寄存器翻译地址的方法和装置
公开(公告)号：US5640528A
公开(公告)日：1997-06-17
申请号：US469798
申请日：1995-06-06
申请人： Kevin Harney , David L. Sprague
发明人： Kevin Harney , David L. Sprague
IPC分类号： G06F9/30 , G06F9/38 , G06F12/02 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0284 , G06F9/30072 , G06F9/30149 , G06F9/3816 , G06F9/3863 , G06F9/3885
摘要： A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as a system address space, are described. Data alignment signal determinations based on comparisons between destination and source addresses permit automatic replacement of virtual addresses with actual physical addresses to permit direct data transfer between devices. In one embodiment, the apparatus for translating comprises a processor; a page table having a mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive comparison values in the comparison value register until a match comparison value is found. A programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress. The programmable replacement values, which correspond to programable map windows, permit the programmable mapping of virtual addresses into different predetermined regions of system virtual address space.
摘要翻译：描述了用于将诸如处理器地址空间的第一地址空间中的第一地址转换到诸如系统地址空间的第二地址空间中的第二地址的方法和装置。基于目的地址和源地址之间的比较的数据对准信号确定允许使用实际物理地址自动替换虚拟地址，以允许设备之间的直接数据传输。在一个实施例中，用于翻译的装置包括处理器; 具有掩模寄存器，比较值寄存器和替换值寄存器的页表; 以及耦合到比较值寄存器和替换值寄存器的比较器。使用翻译掩码寄存器内的可编程掩码来分割虚拟地址。第一子地址包括第一地址的比特的子集，第二子地址包括第一地址的剩余比特。第一个子地址在转换掩码寄存器中用可编程掩码值屏蔽，并通过比较器与比较值寄存器中的连续比较值进行比较，直到找到匹配比较值。对应于匹配比较值的替换值寄存器中的可编程替换值与第二子地址相连。对应于可编程地图窗口的可编程替换值允许将虚拟地址可编程映射到系统虚拟地址空间的不同预定区域。

4. 发明授权

US5548793A System for controlling arbitration using the memory request signal types generated by the plurality of datapaths 失效
标题翻译：用于使用由多个数据路径生成的存储器请求信号类型来控制仲裁的系统
公开(公告)号：US5548793A
公开(公告)日：1996-08-20
申请号：US230899
申请日：1994-04-21
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F13/00 , G06F15/16
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to grant to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.
摘要翻译：一种用于在存储器请求之间进行仲裁的系统和方法。根据优选实施例，系统包括全局存储器和多个数据路径。每个数据路径包括用于执行指令序列的指令并根据指令提供多个存储器请求信号类型的数据路径处理器，其中多个存储器请求信号类型包括指令存储器请求信号，标量存储器请求信号，输入和先出存储器请求信号，统计解码器存储器请求信号和块传送存储器请求信号。每个数据路径还包括本地存储器，用于在本地存储器和全局存储器之间传送数据的全局端口，以及包括用于在本地存储器和数据路口处理器之间传送数据的第一和第二本地端口的双端口，其中第一和第二本地端口允许在本地存储器和数据路径处理器之间同时传输数据。该系统包括耦合到全局存储器的数据总线，用于将数据传送到全局存储器和从全局存储器传送数据;以及传输控制器，用于通过数据总线控制本地存储器和全局存储器之间的块传输和标量数据传输，并且用于在竞争中进行仲裁根据由多个数据路径的数据路径生成的存储器请求信号的信号类型，多个数据路径的数据路径被授权给对数据总线的选择的数据路径访问。

5. 发明授权

US5047975A Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode 失效
标题翻译：具有对特定模式启用的溢出检测和替换的双模式加法器电路
公开(公告)号：US5047975A
公开(公告)日：1991-09-10
申请号：US121022
申请日：1987-11-16
申请人： Michael F. Patti , Nicola J. Fedele , Kevin Harney , Allen H. Simon
发明人： Michael F. Patti , Nicola J. Fedele , Kevin Harney , Allen H. Simon
IPC分类号： G06F7/50 , G06F7/505 , G06F7/506 , H04N7/26
CPC分类号： G06F7/505 , G06F9/30036 , G06F2207/3828 , G06F7/49921
摘要： A video signal processor includes circuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuitry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.
摘要翻译：视频信号处理器包括可由模式控制信号调节的电路，以作为单个16位加法器或两个八位加法器运行。电路包括两个八位加法器，每个加法器都具有输入输入端和输出输出端。一个加法器的输出输出端子通过与门选择性地耦合到另一个加法器的进位输入端。与门由模式控制信号控制。在电路作为两个八位加法器工作的模式下，包括附加电路以检测可能超过零到255范围的有效值的输出值，并使这些无效值在零或255饱和。

6. 发明授权

US5517665A System for controlling arbitration using the memory request signal types generated by the plurality of datapaths having dual-ported local memory architecture for simultaneous data transmission 失效
标题翻译：用于使用由具有双端口本地存储器架构的多个数据路径生成的存储器请求信号类型来控制仲裁的系统，用于同时数据传输
公开(公告)号：US5517665A
公开(公告)日：1996-05-14
申请号：US230915
申请日：1994-04-21
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F15/16 , G06F13/00
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to gram to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.
摘要翻译：一种用于处理数据的系统和方法。根据优选实施例，系统包括全局存储器和多个数据路径。每个数据路径包括用于执行指令序列的指令并根据指令提供多个存储器请求信号类型的数据路径处理器，本地存储器，用于在本地存储器和全局存储器之间传送数据的全局端口，以及双重端口包括用于在本地存储器和数据路径处理器之间传送数据的第一和第二本地端口，其中第一和第二本地端口允许在本地存储器和数据路径处理器之间同时传输数据。该系统包括耦合到全局存储器的数据总线，用于将数据传送到全局存储器和从全局存储器传送数据;以及传输控制器，用于通过数据总线控制本地存储器和全局存储器之间的块传输和标量数据传输，并且用于在竞争中进行仲裁根据由多个数据路径的数据路径生成的存储器请求信号的信号类型，将多个数据路径的数据路径克化为对数据总线的选择的数据路径访问。

7. 发明授权

US5446839A Method for controlling dataflow between a plurality of circular buffers 失效
标题翻译：用于控制多个循环缓冲器之间的数据流的方法
公开(公告)号：US5446839A
公开(公告)日：1995-08-29
申请号：US67858
申请日：1993-05-26
申请人： David Dea , Gary Loeser , Kevin Harney
发明人： David Dea , Gary Loeser , Kevin Harney
IPC分类号： G06F15/17 , H04N7/26 , H04N7/50 , G06F15/16
CPC分类号： G06F15/17 , H04N19/42 , H04N19/423 , H04N19/61
摘要： A video processor system has memory locations for storing images including a buffer block of memory locations. Two separate video processors within the system read and write the buffer block while performing video processor functions. Each of the two video processors has its own read pointer and its own write pointer for indicating locations within the buffer block where it is currently reading or writing an image which it is processing. Both sets of read and write pointers advance through the buffer block as the images are processed. When the pointers reach the end of the buffer block they wrap around to the beginning thereby defining circular buffers. The operations of the two video processors, as well as the reading, advancing, and adjusting of the pointers, is adapted to cause the circular buffers to occupy the same physical memory locations simultaneously.
摘要翻译：视频处理器系统具有用于存储包括存储器位置的缓冲块的图像的存储器位置。系统中的两个独立的视频处理器在执行视频处理器功能时读取和写入缓冲区块。两个视频处理器中的每一个具有其自己的读取指针和它自己的写入指针，用于指示缓冲器块当前正在读取或写入正在处理的图像的位置。当处理图像时，两组读写指针都将通过缓冲区块进行。当指针到达缓冲区块的末尾时，它们循环到起始点，从而定义循环缓冲区。两个视频处理器的操作以及指针的读取，前进和调整适于使循环缓冲器同时占据相同的物理存储器位置。

8. 发明授权

US4881194A Stored-program controller for equalizing conditional branch delays 失效
标题翻译：存储程序控制器，用于均衡条件分支延迟
公开(公告)号：US4881194A
公开(公告)日：1989-11-14
申请号：US121820
申请日：1987-11-16
申请人： David L. Sprague , Kevin Harney , Allen H. Simon , Herbert H. Taylor, Jr.
发明人： David L. Sprague , Kevin Harney , Allen H. Simon , Herbert H. Taylor, Jr.
IPC分类号： G06F9/26
CPC分类号： G06F9/267
摘要： A video signal processor includes a stored-program controller which concurrently reads two instruction values from a program memory during each instruction cycle. The next instruction used by the video signal processor is selected from between these two values. If the current instruction indicates a conditional branch operation, the value of one of a plurality of conditions internal to the video signal processor determines which of these two instructions is selected. Otherwise, a value provided by the current instruction itself determines which of the two instructions is selected. This configuration of the stored program controller implements a conditional branch facility in which there is no delay in fetching an instruction for either value of the selected condition.
摘要翻译：视频信号处理器包括存储程序控制器，其在每个指令周期期间同时从程序存储器读取两个指令值。从这两个值之间选择视频信号处理器使用的下一条指令。如果当前指令指示条件分支操作，则视频信号处理器内部的多个条件之一的值确定选择了这两个指令中的哪一个。否则，由当前指令本身提供的值确定选择了两个指令中的哪一个。存储的程序控制器的这种配置实现条件分支设施，其中在为所选择的条件的任一值获取指令时没有延迟。

9. 发明授权

US4823201A Processor for expanding a compressed video signal 失效
标题翻译：用于扩展压缩视频信号的处理器
公开(公告)号：US4823201A
公开(公告)日：1989-04-18
申请号：US121753
申请日：1987-11-16
申请人： Allen H. Simon , David L. Sprague , John M. Keith , Michael F. Patti , Kevin Harney , Lawrence D. Ryan , Nicola J. Fedele , Brian Astle
发明人： Allen H. Simon , David L. Sprague , John M. Keith , Michael F. Patti , Kevin Harney , Lawrence D. Ryan , Nicola J. Fedele , Brian Astle
IPC分类号： G06T9/00 , H04N7/32 , H04N7/13
CPC分类号： H04N19/50
摘要： A parallel-pipeline video signal processing system is disclosed which includes a statistical decoder, an arithmetic and logic unit and a pixel interpolator which operate in parallel under the control of sequencing circuitry to expand a compressed video signal. The video signal may have been developed using a variety of compression techniques including Huffman-type statistical encoding.
摘要翻译：公开了一种并行流水线视频信号处理系统，其包括统计解码器，算术和逻辑单元以及在排序电路的控制下并行操作以扩展压缩视频信号的像素内插器。可以使用包括霍夫曼型统计编码的各种压缩技术来开发视频信号。

10. 发明授权

US5682208A Motion estimation with efficient block matching 失效
标题翻译：运动估计与有效的块匹配
公开(公告)号：US5682208A
公开(公告)日：1997-10-28
申请号：US332828
申请日：1994-10-31
申请人： Kevin Harney
发明人： Kevin Harney
IPC分类号： H04N5/14 , H04N7/26 , H04N7/36
CPC分类号： H04N5/145 , H04N19/433 , H04N19/51
摘要： A computer-implemented method for encoding image signals. According to a preferred embodiment of the invention, a plurality of search blocks is selected in accordance with the location of a reference block of a current frame. A plurality of words corresponding to the plurality of search blocks is read from a memory device. A difference measurement for each search block of the plurality of search blocks with respect to the reference block is determined from the plurality of words and from the reference block.
摘要翻译：一种用于编码图像信号的计算机实现的方法。根据本发明的优选实施例，根据当前帧的参考块的位置来选择多个搜索块。从存储装置读取与多个搜索块对应的多个字。从多个单词和参考块确定多个搜索块中相对于参考块的每个搜索块的差值测量。

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