专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07382776B1 Performing block storage virtualization at a switch 有权
标题翻译：在交换机上执行块存储虚拟化
公开(公告)号：US07382776B1
公开(公告)日：2008-06-03
申请号：US10414889
申请日：2003-04-15
申请人： Litko Chan , Richard D. Reohr, Jr. , Joseph I. Chamdani
发明人： Litko Chan , Richard D. Reohr, Jr. , Joseph I. Chamdani
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L67/1097 , H04L45/7453 , H04L49/253 , H04L49/35
摘要： Routing a data packet includes receiving at a switch a data packet from a storage client. The data packet is associated with a destination identifier identifying a virtual target, where the virtual target is accessible by the storage client. A storage resource identifier corresponding to the destination identifier is determined according to a forwarding table at the switch. The data packet is routed according to the storage resource identifier.
摘要翻译：路由数据分组包括在交换机处接收来自存储客户端的数据分组。数据分组与标识虚拟目标的目的地标识符相关联，虚拟目标可由存储客户端访问。根据交换机的转发表确定与目的地标识符对应的存储资源标识符。根据存储资源标识符路由数据包。

2. 发明授权

US07460528B1 Processing data packets at a storage service module of a switch 有权
标题翻译：在交换机的存储服务模块处理数据包
公开(公告)号：US07460528B1
公开(公告)日：2008-12-02
申请号：US10414891
申请日：2003-04-15
申请人： Joseph I. Chamdani , Litko Chan , Richard D. Reohr, Jr. , Wilson K. Yee
发明人： Joseph I. Chamdani , Litko Chan , Richard D. Reohr, Jr. , Wilson K. Yee
IPC分类号： H04L12/28 , H04L12/50 , H04L12/56
CPC分类号： H04L67/1097
摘要： Routing a data packet of an information unit sequence includes receiving at a switch a data packet of an information unit sequence of a block storage exchange from a storage client, where the sequence is associated with a source identifier and a target identifier identifying a target. A storage resource identifier corresponding to the target identifier is determined according to a forwarding table. A sequence identifier is associated with the source identifier, where the sequence identifier corresponds to the target. The source identifier and the sequence identifier are recorded at a context table, and the data packet is routed according to the storage resource identifier.
摘要翻译：路由信息单元序列的数据分组包括在交换机处接收来自存储客户端的块存储交换的信息单元序列的数据分组，其中该序列与源标识符和标识目标的目标标识符相关联。根据转发表确定与目标标识符对应的存储资源标识符。序列标识符与源标识符相关联，其中序列标识符对应于目标。源标识符和序列标识符被记录在上下文表中，并且根据存储资源标识符路由数据分组。

3. 发明授权

US07088735B1 Processing data packets in a multiple protocol system area network 有权
标题翻译：在多协议系统区域网络中处理数据包
公开(公告)号：US07088735B1
公开(公告)日：2006-08-08
申请号：US10071969
申请日：2002-02-05
申请人： Richard D. Reohr, Jr. , Joseph E. Pelissier , Joseph I. Chamdani
发明人： Richard D. Reohr, Jr. , Joseph E. Pelissier , Joseph I. Chamdani
IPC分类号： H04L12/26
CPC分类号： H04L41/0226 , H04L69/03
摘要： Processing a data packet in a multiple protocol system area network is disclosed. A paddle card comprising a first paddle card that supports a first communication protocol or a second paddle card that supports a second communication protocol is received. The communication protocol supported by the received paddle card is identified. Data packets from the received paddle card are processed according to the identified communication protocol.
摘要翻译：公开了在多协议系统区域网络中处理数据分组。接收包括支持第一通信协议的第一拨号卡或支持第二通信协议的第二拨号卡的拨号卡。识别接收到的卡片支持的通信协议。根据所识别的通信协议来处理来自接收到的所述桨卡的数据分组。

4. 发明授权

US07433351B1 Isolation of data, control, and management traffic in a storage area network 失效
标题翻译：隔离存储区域网络中的数据，控制和管理流量
公开(公告)号：US07433351B1
公开(公告)日：2008-10-07
申请号：US10153512
申请日：2002-05-22
申请人： Joseph E. Pelissier , Vikas Deolaliker , Joseph I. Chamdani , Litko Chan , Gurumurthy D. Ramkumar , Rajasekhar Cherabuddi
发明人： Joseph E. Pelissier , Vikas Deolaliker , Joseph I. Chamdani , Litko Chan , Gurumurthy D. Ramkumar , Rajasekhar Cherabuddi
IPC分类号： H04L12/28 , H04L12/56 , H04J3/24 , G06F15/16
CPC分类号： H04L49/351 , H04L67/1097
摘要： Switching data packets includes forwarding first data packets to a first port that is associated with a first domain. Second data packets are forwarded to a second port that is associated with a second domain. The first data packets are managed using a first management subsystem of a service processor card, and the second data packets are managed using a second management subsystem of the service processor card.
摘要翻译：切换数据分组包括将第一数据分组转发到与第一域相关联的第一端口。第二数据分组被转发到与第二域相关联的第二端口。使用服务处理器卡的第一管理子系统管理第一数据分组，并且使用服务处理器卡的第二管理子系统管理第二数据分组。

5. 发明申请

US20110099155A1 FAST BATCH LOADING AND INCREMENTAL LOADING OF DATA INTO A DATABASE 有权
标题翻译：快速批量加载和数据加载到数据库中
公开(公告)号：US20110099155A1
公开(公告)日：2011-04-28
申请号：US12984284
申请日：2011-01-04
申请人： James Shau , Krishnan Meiyyappan , Hung Tran , Ravi Krishnamurthy , Kapil Surlaker , Jeremy Branscome , Joseph I. Chamdani
发明人： James Shau , Krishnan Meiyyappan , Hung Tran , Ravi Krishnamurthy , Kapil Surlaker , Jeremy Branscome , Joseph I. Chamdani
IPC分类号： G06F17/30
CPC分类号： G06F17/30595
摘要： Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.
摘要翻译：本发明的实施例提供数据批量和增量加载到数据库中。在本发明中，装载机基础设施利用机器码数据库指令和硬件加速来将加载操作与I / O操作并行化。大型的硬件加速器内存用作加载进程的分段缓存。加载过程还包括一个索引分析阶段，可以对所创建的索引进行平衡分区，以允许流水线负载。在提供查询时也可以执行在线增量加载过程。

6. 发明申请

US20090254516A1 ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE INDEXING AND REPLICATED REORDERED COLUMNS 有权
标题翻译：基于硬件兼容的索引和已更新的列进行存储数据库中的数据访问
公开(公告)号：US20090254516A1
公开(公告)日：2009-10-08
申请号：US12099133
申请日：2008-04-07
申请人： Krishnan Meiyyappan , Liuxi Yang , Jeremy Branscome , Michael Corwin , Ravi Krishnamurthy , Kapil Surlaker , James Shau , Joseph I. Chamdani
发明人： Krishnan Meiyyappan , Liuxi Yang , Jeremy Branscome , Michael Corwin , Ravi Krishnamurthy , Kapil Surlaker , James Shau , Joseph I. Chamdani
IPC分类号： G06F7/06 , G06F17/30
CPC分类号： G06F17/30442 , G06F17/30094 , G06F17/30315 , G06F17/30492 , G06F17/30504
摘要： Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.
摘要翻译：本发明的实施例提供数据库的硬件友好索引。特别地，正向和反向索引被用于允许轻松地遍历主键到外键关系。被称为命中列表的新颖结构还允许在硬件中容易地扫描各种索引。提供组索引，用于复杂组密钥定义的灵活支持，如日期范围索引和文本索引。还可以将复制的重新排列（RRC）添加到组索引中以将随机I / O模式转换为仅需要的列元素的顺序I / O。

7. 发明授权

US07587581B2 Multiple-thread processor with in-pipeline, thread selectable storage 有权
标题翻译：多线程处理器具有管线，线程可选存储
公开(公告)号：US07587581B2
公开(公告)日：2009-09-08
申请号：US11710112
申请日：2007-02-23
申请人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
发明人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F9/38
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
摘要翻译：处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间，并增加执行时间的比例。垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。在垂直多线程中，多个硬件线程共享相同的处理器管道。在支持多线程的操作系统中，硬件线程通常是进程，轻量级进程，本机线程等。水平多线程增加了处理器电路结构内的并行性，例如在构成单片处理器的单个集成电路管芯内。为了在一些处理器实施例中进一步增加系统并行性，在单个管芯中形成多个处理器核。通过技术进步降低了处理器核心尺寸，从而获得片上多处理器水平线程的进步。

8. 发明授权

US07539929B1 Error correction for data communication 失效
标题翻译：数据通信纠错
公开(公告)号：US07539929B1
公开(公告)日：2009-05-26
申请号：US11154886
申请日：2005-06-15
申请人： Ulrich Stern , Joseph I. Chamdani , Yu Fang , Liuxi Yang
发明人： Ulrich Stern , Joseph I. Chamdani , Yu Fang , Liuxi Yang
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H03M13/13
摘要： Generating a check matrix includes defining a generator function operable to yield check bits associated with a word. A set of primitive elements is calculated from the generator function. A set of check matrix columns is generated, where each check matrix column includes a matrix having a subset of the set of primitive elements. A check matrix is generated from a subset of the set of check matrix columns, where the check matrix yields a syndrome that comprises an error pattern for the word. The check matrix is reported.
摘要翻译：生成校验矩阵包括定义发生器功能，其可操作以产生与单词相关联的校验位。从生成函数计算一组原始元素。生成一组校验矩阵列，其中每个校验矩阵列包括具有该组原始元素的子集的矩阵。从校验矩阵列集合的子集生成校验矩阵，其中校验矩阵产生包括该单词的错误模式的校正子。报告校验矩阵。

9. 发明授权

US07133416B1 Converting data signals in a multiple communication protocol system area network 有权
标题翻译：在多个通信协议系统区域网络中转换数据信号
公开(公告)号：US07133416B1
公开(公告)日：2006-11-07
申请号：US10091916
申请日：2002-03-05
申请人： Joseph I. Chamdani , Matthew S. Rogge , Peter Gunadisastra , Jayarama N. Shenoy , Tsuei-chieh Chiu
发明人： Joseph I. Chamdani , Matthew S. Rogge , Peter Gunadisastra , Jayarama N. Shenoy , Tsuei-chieh Chiu
IPC分类号： H04L12/66
CPC分类号： H04L12/66
摘要： Converting data signals includes determining whether a coupled interface converter paddle coupled to a serdes is a first interface converter paddle or a second interface converter paddle. The first interface converter paddle is associated with a first communication protocol, and the second interface converter paddle is associated with a second communication protocol. The communication protocol associated with the coupled interface converter paddle is identified. Data signals are received from the coupled interface converter paddle, and deserialized according to the identified communication protocol.
摘要翻译：转换数据信号包括确定耦合到serdes的耦合接口转换器桨是否是第一接口转换器桨或第二接口转换器桨。第一接口转换器桨与第一通信协议相关联，并且第二接口转换器桨与第二通信协议相关联。识别与耦合的接口转换器板相关联的通信协议。从耦合的接口转换器桨接收数据信号，并根据所识别的通信协议反序列化。

10. 发明授权

US06351808B1 Vertically and horizontally threaded processor with multidimensional storage for storing thread data 有权
标题翻译：垂直和水平线程处理器，具有用于存储线程数据的多维存储
公开(公告)号：US06351808B1
公开(公告)日：2002-02-26
申请号：US09309731
申请日：1999-05-11
申请人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
发明人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F946
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3013 , G06F9/3802 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： A processor includes a “four-dimensional” register structure in which register file structures are replicated by N for vertical threading in combination with a three-dimensional storage circuit. The multi-dimensional storage is formed by constructing a storage, such as a register file or memory, as a plurality of two-dimensional storage planes.
摘要翻译：处理器包括一个“四维”寄存器结构，其中寄存器堆栈结构由N复制用于与三维存储电路结合的垂直线程。多维存储器通过构造诸如寄存器文件或存储器的存储器来形成为多个二维存储平面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式