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1. 发明授权

US6051493A Process for protecting bonded components from plating shorts 失效
标题翻译：保护接合部件免受镀层短路的工艺
公开(公告)号：US6051493A
公开(公告)日：2000-04-18
申请号：US323410
申请日：1994-10-14
申请人： Lisa A. Tarte , Wayne L. Bonde , Paul G. Carey , Robert J. Contolini , Anthony M. McCarthy
发明人： Lisa A. Tarte , Wayne L. Bonde , Paul G. Carey , Robert J. Contolini , Anthony M. McCarthy
IPC分类号： H01L21/60 , H01L21/44
CPC分类号： H01L24/80 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14
摘要： A method which protects the region between a component and the substrate onto which the components is bonded using an electrically insulating fillet of photoresist. The fillet protects the regions from subsequent plating with metal and therefore shorting the plated conductors which run down the sides of the component and onto the substrate.
摘要翻译：使用光刻胶的电绝缘圆角来保护组件与组件与基板之间的区域的方法。圆角保护区域免受金属的后续镀覆，从而使从元器件的侧面向下延伸到衬底上的电镀导体短路。

2. 发明授权

US5486234A Removal of field and embedded metal by spin spray etching 失效
标题翻译：通过旋转喷涂蚀刻去除场和嵌入金属
公开(公告)号：US5486234A
公开(公告)日：1996-01-23
申请号：US375054
申请日：1995-01-19
申请人： Robert J. Contolini , Steven T. Mayer , Lisa A. Tarte
发明人： Robert J. Contolini , Steven T. Mayer , Lisa A. Tarte
IPC分类号： H01L21/3213 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76838 , H01L21/32134
摘要： A process of removing both the field metal, such as copper, and a metal, such as copper, embedded into a dielectric or substrate at substantially the same rate by dripping or spraying a suitable metal etchant onto a spinning wafer to etch the metal evenly on the entire surface of the wafer. By this process the field metal is etched away completely while etching of the metal inside patterned features in the dielectric at the same or a lesser rate. This process is dependent on the type of chemical etchant used, the concentration and the temperature of the solution, and also the rate of spin speed of the wafer during the etching. The process substantially reduces the metal removal time compared to mechanical polishing, for example, and can be carried out using significantly less expensive equipment.
摘要翻译：通过将合适的金属蚀刻剂滴落或喷涂到旋转的晶片上以均匀地蚀刻金属，以基本上相同的速率将现场金属（例如铜）和金属（例如铜）两者嵌入电介质或基底中的步骤晶片的整个表面。通过该处理，在以相同或较小的速率蚀刻电介质中的图案化特征内的金属的同时蚀刻完全场地金属。该过程取决于所使用的化学蚀刻剂的类型，溶液的浓度和温度，以及蚀刻期间晶片的旋转速度。例如，与机械抛光相比，该方法显着降低了金属去除时间，并且可以使用显着更便宜的设备进行。

3. 发明授权

US5099311A Microchannel heat sink assembly 失效
标题翻译：微通道散热器组件
公开(公告)号：US5099311A
公开(公告)日：1992-03-24
申请号：US642736
申请日：1991-01-17
申请人： Wayne L. Bonde , Robert J. Contolini
发明人： Wayne L. Bonde , Robert J. Contolini
IPC分类号： F28D9/00 , H01L23/34 , H01L23/44 , H01L23/473
CPC分类号： F28F3/12 , H01L23/345 , H01L23/445 , H01L23/473 , F28F2260/02 , H01L2924/0002
摘要： The present invention provides a microchannel heat sink with a thermal range from cryogenic temperatures to several hundred degrees centigrade. The heat sink can be used with a variety of fluids, such as cryogenic or corrosive fluids, and can be operated at a high pressure. The heat sink comprises a microchannel layer preferably formed of silicon, and a manifold layer preferably formed of glass. The manifold layer comprises an inlet groove and outlet groove which define an inlet manifold and an outlet manifold. The inlet manifold delivers coolant to the inlet section of the microchannels, and the outlet manifold receives coolant from the outlet section of the microchannels. In one embodiment, the manifold layer comprises an inlet hole extending through the manifold layer to the inlet manifold, and an outlet hole extending through the manifold layer to the outlet manifold. Coolant is supplied to the heat sink through a conduit assembly connected to the heat sink. A resilient seal, such as a gasket or an O-ring, is disposed between the conduit and the hole in the heat sink in order to provide a watetight seal. In other embodiments, the conduit assembly may comprise a metal tube which is connected to the heat sink by a soft solder. In still other embodiments, the heat sink may comprise inlet and outlet nipples. The present invention has application in supercomputers, integrated circuits and other electronic devices, and is suitable for cooling materials to superconducting temperatures.
摘要翻译：本发明提供了一种从低温到几百摄氏度的热范围的微通道散热器。散热器可用于各种流体，如低温或腐蚀性流体，并可在高压下运行。散热器包括优选由硅形成的微通道层和优选由玻璃形成的歧管层。歧管层包括限定入口歧管和出口歧管的入口槽和出口槽。入口歧管将冷却剂输送到微通道的入口部分，并且出口歧管从微通道的出口部分接收冷却剂。在一个实施例中，歧管层包括延伸穿过歧管层到入口歧管的入口孔，以及延伸穿过歧管层到出口歧管的出口孔。冷却液通过连接到散热器的导管组件提供给散热器。诸如垫圈或O形环的弹性密封件设置在导管和散热器中的孔之间，以提供密封。在其他实施例中，导管组件可以包括通过软焊料连接到散热器的金属管。在其它实施例中，散热器可以包括入口和出口接头。本发明适用于超级计算机，集成电路和其他电子设备，适用于超导温度下的冷却材料。

4. 发明授权

US6139716A Submicron patterned metal hole etching 失效
标题翻译：亚微米图案金属孔蚀刻
公开(公告)号：US6139716A
公开(公告)日：2000-10-31
申请号：US315387
申请日：1999-05-18
申请人： Anthony M. McCarthy , Robert J. Contolini , Vladimir Liberman , Jeffrey Morse
发明人： Anthony M. McCarthy , Robert J. Contolini , Vladimir Liberman , Jeffrey Morse
IPC分类号： C25F3/12
CPC分类号： C25F3/12
摘要： A wet chemical process for etching submicron patterned holes in thin metal layers using electrochemical etching with the aid of a wetting agent. In this process, the processed wafer to be etched is immersed in a wetting agent, such as methanol, for a few seconds prior to inserting the processed wafer into an electrochemical etching setup, with the wafer maintained horizontal during transfer to maintain a film of methanol covering the patterned areas. The electrochemical etching setup includes a tube which seals the edges of the wafer preventing loss of the methanol. An electrolyte composed of 4:1 water: sulfuric is poured into the tube and the electrolyte replaces the wetting agent in the patterned holes. A working electrode is attached to a metal layer of the wafer, with reference and counter electrodes inserted in the electrolyte with all electrodes connected to a potentiostat. A single pulse on the counter electrode, such as a 100 ms pulse at +10.2 volts, is used to excite the electrochemical circuit and perform the etch. The process produces uniform etching of the patterned holes in the metal layers, such as chromium and molybdenum of the wafer without adversely effecting the patterned mask.
摘要翻译：借助于润湿剂，使用电化学蚀刻在薄金属层中蚀刻亚微米图案化孔的湿法化学方法。在此过程中，待处理的待蚀刻晶片在将经处理的晶片插入电化学蚀刻装置之前，浸入润湿剂（如甲醇）中几秒钟，晶片在转移过程中保持水平，以保持甲醇膜覆盖图案区域。电化学蚀刻装置包括密封晶片边缘的管，防止甲醇损失。将由4:1水：硫酸盐组成的电解液倒入管中，并且电解质代替图案化孔中的润湿剂。将工作电极连接到晶片的金属层上，其中参考电极和对置电极插入电解质中，所有电极连接到恒电位仪。对电极上的单个脉冲，例如+10.2伏特的100ms脉冲，用于激发电化学电路并进行蚀刻。该方法对金属层中的图案化孔进行均匀蚀刻，例如晶片的铬和钼，而不会对图案化掩模产生不利影响。

5. 发明授权

US06162344A Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer 有权
标题翻译：使用可变电流和质量传递电镀半导体晶片以获得均匀的镀层的方法
公开(公告)号：US06162344A
公开(公告)日：2000-12-19
申请号：US393226
申请日：1999-09-09
申请人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
发明人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
IPC分类号： C25D5/18 , C25D7/12 , C25D5/00
CPC分类号： C25D5/18 , C25D7/123 , Y10S205/915
摘要： In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.
摘要翻译：在电镀半导体晶片上的金属层时，电极端子所在的晶片边缘与晶片的中心之间的电阻电压降使得电镀速率在边缘比在中心处更大。作为这种所谓的“终端效应”的结果，镀层倾向于是凹的。通过首先将电流设置在相对低的电平直到电镀层足够厚以使电阻降可忽略，然后增加电流以提高电镀速率来克服该问题。或者，可以使在较高电流下产生的层的部分略微凸起，以补偿在较低电流下产生的层的部分的凹形。这是通过减少靠近晶片边缘的电镀溶液的质量传递来实现的，即在该区域中电镀过程被传质限制。结果，在这些条件下形成的层的部分在晶片的边缘附近更薄。

6. 发明授权

US06261961B1 Adhesion layer for etching of tracks in nuclear trackable materials 失效
标题翻译：用于蚀刻核可追踪材料中的轨道的粘附层
公开(公告)号：US06261961B1
公开(公告)日：2001-07-17
申请号：US09258917
申请日：1999-03-01
申请人： Jeffrey D. Morse , Robert J. Contolini
发明人： Jeffrey D. Morse , Robert J. Contolini
IPC分类号： H01L21311
CPC分类号： H01L21/32139
摘要： A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO2), silicon nitride (SiNx), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.
摘要翻译：在核可追溯材料如聚碳酸酯（LEXAN）中形成宽度为100-200nm的核轨道的方法，而不会引起LEXAN的分层。该方法利用具有惰性氧化物的粘合膜，其允许轨道被充分地扩大到> 200nm，而不会使核可追踪材料分层。粘合膜可以由诸如二氧化硅（SiO 2），氮化硅（SiN x）和氧化铝（SiO 2）等具有稳定表面的电介质组成的诸如Cr，Ni，Au，Pt或Ti的金属组成， AlO）。粘附膜可以沉积在栅极金属层的顶部，或者如果粘附膜的性质足够，则可以将其用作栅极层。通过标准技术如溅射或蒸发来实现粘附膜的沉积。

7. 发明授权

US6110346A Method of electroplating semicoductor wafer using variable currents and mass transfer to obtain uniform plated layer 有权
标题翻译：使用可变电流和质量传递电镀半导体晶片的方法以获得均匀的镀层
公开(公告)号：US6110346A
公开(公告)日：2000-08-29
申请号：US393848
申请日：1999-09-09
申请人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
发明人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
IPC分类号： C25D5/18 , C25D7/12 , C25D5/00 , C25D5/16 , C25D9/04
CPC分类号： C25D5/18 , C25D7/123 , Y10S205/915
摘要： In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.
摘要翻译：在电镀半导体晶片上的金属层时，电极端子所在的晶片边缘与晶片的中心之间的电阻电压降使得电镀速率在边缘比在中心处更大。作为这种所谓的“终端效应”的结果，镀层倾向于是凹的。通过首先将电流设置在相对低的电平直到电镀层足够厚以使电阻降可忽略，然后增加电流以提高电镀速率来克服该问题。或者，可以使在较高电流下产生的层的部分略微凸起，以补偿在较低电流下产生的层的部分的凹形。这是通过减少靠近晶片边缘的电镀溶液的质量传递来实现的，即在该区域中电镀过程被传质限制。结果，在这些条件下形成的层的部分在晶片的边缘附近更薄。

8. 发明授权

US6033583A Vapor etching of nuclear tracks in dielectric materials 失效
标题翻译：电介质材料中核磁道的蒸气蚀刻
公开(公告)号：US6033583A
公开(公告)日：2000-03-07
申请号：US851258
申请日：1997-05-05
申请人： Ronald G. Musket , John D. Porter , James M. Yoshiyama , Robert J. Contolini
发明人： Ronald G. Musket , John D. Porter , James M. Yoshiyama , Robert J. Contolini
IPC分类号： C03C15/00 , C03C17/34 , C03C21/00
CPC分类号： C03C17/3417 , C03C15/00 , C03C17/3482 , C03C2218/33
摘要： A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant. The 20-1000 nm diameter holes resulting from the vapor etching process can be useful as molds for electroplating nanometer-sized filaments, etching gate cavities for deposition of nano-cones, developing high-aspect ratio holes in trackable resists, and as filters for a variety of molecular-sized particles in virtually any liquid or gas by selecting the dielectric material that is compatible with the liquid or gas of interest.
摘要翻译：用于产生高纵横比（即，远大于直径的长度）的电介质材料中的核轨道的蒸汽蚀刻，已经暴露于高能原子粒子的电介质材料中的孤立的圆柱形孔。该方法包括清洁被跟踪材料的表面并将清洁的表面暴露于合适蚀刻剂的蒸汽。独立控制蒸汽和跟踪材料的温度提供了单独改变潜在轨道区域和非轨道材料的蚀刻速率的手段。通常，跟踪区域以比非跟踪区域更大的速率蚀刻。此外，通过随后在液体蚀刻剂中浸渍，可以使蒸气蚀刻的孔扩大和平滑。由气相蚀刻工艺产生的20-1000nm直径的孔可用作用于电镀纳米尺寸丝的模具，用于沉积纳米锥体的蚀刻门腔，在可追踪抗蚀剂中显影高纵横比孔，以及用于通过选择与感兴趣的液体或气体相容的电介质材料，实际上任何液体或气体中的各种分子大小的颗粒。

9. 发明授权

US5256565A Electrochemical planarization 失效
标题翻译：电化学平面化
公开(公告)号：US5256565A
公开(公告)日：1993-10-26
申请号：US348982
申请日：1989-05-08
申请人： Anthony F. Bernhardt , Robert J. Contolini
发明人： Anthony F. Bernhardt , Robert J. Contolini
IPC分类号： H01L21/28 , C23C18/31 , H01L21/3063 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L21/465
CPC分类号： H01L21/7684 , H01L21/32115
摘要： In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.
摘要翻译：在用于制造用于集成电路结构的平坦化薄膜金属互连件的工艺中，通过电抛光，离子铣削或其它程序将平坦化金属层回蚀刻到下面的介电层。电抛光将处理时间从几小时缩短到几分钟，并允许批量处理多个晶圆。蚀刻后的平坦化薄膜互连与电介质层齐平。

10. 发明授权

US5096550A Method and apparatus for spatially uniform electropolishing and electrolytic etching 失效
标题翻译：用于空间均匀电解和电解蚀刻的方法和装置
公开(公告)号：US5096550A
公开(公告)日：1992-03-17
申请号：US597225
申请日：1990-10-15
申请人： Steven T. Mayer , Robert J. Contolini , Anthony F. Bernhardt
发明人： Steven T. Mayer , Robert J. Contolini , Anthony F. Bernhardt
IPC分类号： C25F3/02 , C25F3/16 , C25F7/00
CPC分类号： C25F7/00 , C25F3/02 , C25F3/16 , Y10S204/07
摘要： In an electropolishing or electrolytic etching apparatus the anode is separated from the cathode to prevent bubble transport to the anode and to produce a uniform current distribution at the anode by means of a solid nonconducting anode-cathode barrier. The anode extends into the top of the barrier and the cathode is outside the barrier. A virtual cathode hole formed in the bottom of the barrier below the level of the cathode permits current flow while preventing bubble transport. The anode is rotatable and oriented horizontally facing down. An extended anode is formed by mounting the workpiece in a holder which extends the electropolishing or etching area beyond the edge of the workpiece to reduce edge effects at the workpiece. A reference electrode controls cell voltage. Endpoint detection and current shut-off stop polishing. Spatially uniform polishing or etching can be rapidly performed.
摘要翻译：在电解抛光或电解蚀刻装置中，阳极与阴极分离，以防止气泡传输到阳极，并通过固体非导电阳极 - 阴极屏障在阳极处产生均匀的电流分布。阳极延伸到屏障的顶部，阴极在屏障外。形成在阴极底部的阴极底部的虚拟阴极孔允许电流流动，同时防止气泡输送。阳极可旋转并水平定向朝下。扩展阳极通过将工件安装在将电解抛光或蚀刻区域延伸超过工件边缘的保持器中形成，以减少工件的边缘效应。参考电极控制电池电压。端点检测和电流切断停止抛光。可以快速进行空间均匀的抛光或蚀刻。

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