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1. 发明申请

US20110296216A1 INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB 有权
标题翻译：处理器和输入/输出总线的集成
公开(公告)号：US20110296216A1
公开(公告)日：2011-12-01
申请号：US12791836
申请日：2010-06-01
申请人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
发明人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
摘要翻译：描述了用于集成处理器和输入/输出集线器的方法和装置。在一个实施例中，边带信号可能导致处理器或集成I / O逻辑的电源管理状态的改变。单个集成电路管芯可以包括处理器和集成I / O逻辑。还公开了其他实施例。

2. 发明授权

US08850250B2 Integration of processor and input/output hub 有权
标题翻译：处理器和输入/输出集线器的集成
公开(公告)号：US08850250B2
公开(公告)日：2014-09-30
申请号：US12791836
申请日：2010-06-01
申请人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
发明人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
摘要翻译：描述了用于集成处理器和输入/输出集线器的方法和装置。在一个实施例中，边带信号可能导致处理器或集成I / O逻辑的电源管理状态的改变。单个集成电路管芯可以包括处理器和集成I / O逻辑。还公开了其他实施例。

3. 发明授权

US08782456B2 Dynamic and idle power reduction sequence using recombinant clock and power gating 有权
标题翻译：使用重组时钟和电源门控的动态和空闲功率降低序列
公开(公告)号：US08782456B2
公开(公告)日：2014-07-15
申请号：US12978452
申请日：2010-12-24
申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
发明人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
摘要翻译：描述了使用重组时钟和/或电源门控的用于动态和/或空闲功率降低序列的方法和装置。在一个实施例中，集成输入/输出（IIO）逻辑的至少一部分是基于功率降低序列进入较低功耗状态。还公开了其他实施例。

4. 发明申请

US20110296222A1 DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING 有权
标题翻译：使用重构时钟和功率增益的动态和空闲功率降低序列
公开(公告)号：US20110296222A1
公开(公告)日：2011-12-01
申请号：US12978452
申请日：2010-12-24
申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
发明人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
摘要翻译：描述了使用重组时钟和/或电源门控的用于动态和/或空闲功率降低序列的方法和装置。在一个实施例中，集成输入/输出（IIO）逻辑的至少一部分是基于功率降低序列进入较低功耗状态。还公开了其他实施例。

5. 发明授权

US09146610B2 Throttling integrated link 有权
标题翻译：节流综合链接
公开(公告)号：US09146610B2
公开(公告)日：2015-09-29
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32 , G06F13/42
CPC分类号： G06F13/4059 , G06F1/3206 , G06F1/3253 , G06F13/4027 , G06F13/4286 , G06F13/4295 , Y02B60/1228 , Y02B60/1235 , Y02D10/151
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
摘要翻译：描述了用于对与处理器集成在同一裸片上的接口进行节流的方法和装置。在一个实施例中，来自集成输入/输出集线器（例如，集成在与处理器相同的芯片上）的信号引起耦合在IIO和输入/输出（IO）设备之间的链路的节流。还公开了其他实施例。

6. 发明授权

US09110666B2 Throttling integrated link 有权
公开(公告)号：US09110666B2
公开(公告)日：2015-08-18
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32 , G06F13/42
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.

7. 发明申请

US20120079159A1 Throttling Integrated Link 有权
标题翻译：节流综合链路
公开(公告)号：US20120079159A1
公开(公告)日：2012-03-29
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F13/36 , G06F13/14
CPC分类号： G06F13/4059 , G06F1/3206 , G06F1/3253 , G06F13/4027 , G06F13/4286 , G06F13/4295 , Y02B60/1228 , Y02B60/1235 , Y02D10/151
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
摘要翻译：描述了用于对与处理器集成在同一裸片上的接口进行节流的方法和装置。在一个实施例中，来自集成输入/输出集线器（例如，集成在与处理器相同的芯片上）的信号引起耦合在IIO和输入/输出（IO）设备之间的链路的节流。还公开了其他实施例。

8. 发明授权

US07093079B2 Snoop filter bypass 有权
标题翻译：窥探过滤器旁路
公开(公告)号：US07093079B2
公开(公告)日：2006-08-15
申请号：US10323200
申请日：2002-12-17
申请人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
发明人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/082
摘要： Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.
摘要翻译：描述了用于处理包括多个高速缓存节点的计算设备的相干请求的机器可读介质，方法和装置。在一些实施例中，相干开关可以从请求的高速缓存节点接收对一行存储器的相干请求。基于是否启用窥探过滤器旁路模式，相干交换机可以进一步向一个或多个非请求高速缓存节点发出窥探请求。特别地，当不在窥探过滤器旁路模式时，相干开关可以从窥探过滤器获得一致性数据，并且可以基于从窥探过滤器获得的一致性数据向0个或更多个非请求缓存节点发出窥探请求。此外，在窥探过滤器旁路模式中的相干交换机可以绕过窥探过滤器并且可以向所有不请求的缓存代理发出窥探请求。

9. 发明授权

US5930486A Method and device for gracious arbitration of access to a computer system resource 失效
标题翻译：用于访问计算机系统资源的亲和仲裁的方法和装置
公开(公告)号：US5930486A
公开(公告)日：1999-07-27
申请号：US707884
申请日：1996-09-09
申请人： Lily Pao Looi , Nitin Borkar , Frank Verhoorn
发明人： Lily Pao Looi , Nitin Borkar , Frank Verhoorn
IPC分类号： G06F13/364 , G06F13/362
CPC分类号： G06F13/364
摘要： A computer system includes a priority arbitration scheme that prevents "hogging" of a bus by a priority agent. The computer system comprises at least one agent, at least one priority agent, a system resource, and a bus coupling the agent, priority agent, and system resource to one another. An arbiter is coupled to the bus, agent, and priority agent to receive request signals from the agent and the priority agent and to grant control of the bus to one of the agent and priority agent for access to the system resource. The priority agent is granted control of the bus whenever the priority agent asserts a request signal, as soon as the bus becomes next available. The priority agent relinquishes control of the bus to the agent, for a predetermined portion of the bus bandwidth, when a request signal is asserted by the agent.
摘要翻译：计算机系统包括优先权仲裁方案，其防止优先代理人对总线进行“占用”。计算机系统包括至少一个代理，至少一个优先级代理，系统资源和将代理，优先级代理和系统资源彼此耦合的总线。仲裁器耦合到总线，代理和优先级代理以从代理和优先级代理接收请求信号，并且将总线的控制权授予代理和优先级代理之一用于访问系统资源。一旦总线变为下一个可用，优先权代理就会在优先权代理人断言一个请求信号时被控制总线。当代理人断言请求信号时，优先权代理将总线的总线放弃到总线带宽的预定部分。

10. 发明申请

US20140281639A1 DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR FASTER BOOT TIME 审中-公开
标题翻译：设备电源管理状态转换延迟延迟更快的启动时间
公开(公告)号：US20140281639A1
公开(公告)日：2014-09-18
申请号：US13838220
申请日：2013-03-15
申请人： Mahesh Wagh , Lily Pao Looi
发明人： Mahesh Wagh , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/325 , G06F1/3275 , G06F1/3278 , G06F1/3287 , G06F9/4418 , G06F13/4265 , G06F13/4282 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/171 , Y02D10/44
摘要： Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与设备电源管理状态转换延迟广告相关的方法和装置，用于更快的启动时间。在一些实施例中，存储单元存储对应于第一代理从低功耗状态退出的必要的转换延迟周期的值。第一代理人将该值写入存储单元，并且第二代理程序在第二代理程序尝试通过链路与第一代理进行通信之前，等待必要的转换延迟周期（在第一代理程序从低功耗状态退出之后）。还公开并要求保护其他实施例。

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