专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08852968B2 STI CMP under polish monitoring 有权
标题翻译： STI CMP在抛光监测下
公开(公告)号：US08852968B2
公开(公告)日：2014-10-07
申请号：US13768870
申请日：2013-02-15
申请人： Liang Li , Zheng Zou , Huang Liu , Alex See
发明人： Liang Li , Zheng Zou , Huang Liu , Alex See
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , G01B2210/56
摘要： Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra.
摘要翻译：提供了使用计算和测量的散射光谱推导氧化物厚度的方法。实施例包括在半导体晶片上沉积氧化物，从半导体晶片的一部分还原氧化物，并使用散射测量法推算残留在该部分内部的氧化物的厚度。实施例还包括通过以下方式推导厚度：计算多个氧化物厚度的散射光谱，产生计算的散射光谱，监测半导体晶片部分内的位置处的散射光谱，将该位置处的所监视的散射光谱与计算出的散射光谱进行比较确定与所述位置处的所监视的散射光谱最接近的匹配计算的散射光谱，以及获得对应于最接近的匹配计算的散射光谱的氧化物厚度。

2. 发明授权

US08492236B1 Step-like spacer profile 有权
标题翻译：阶梯状间隔剖面
公开(公告)号：US08492236B1
公开(公告)日：2013-07-23
申请号：US13348766
申请日：2012-01-12
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/78
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
摘要翻译：通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物，像个人资料实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

3. 发明申请

US20130181259A1 STEP-LIKE SPACER PROFILE 有权
公开(公告)号：US20130181259A1
公开(公告)日：2013-07-18
申请号：US13348766
申请日：2012-01-12
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/6656 , H01L29/78
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
摘要翻译：通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物，像个人资料实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

4. 发明授权

US08569173B2 Methods of protecting elevated polysilicon structures during etching processes 有权
标题翻译：在蚀刻过程中保护高架多晶硅结构的方法
公开(公告)号：US08569173B2
公开(公告)日：2013-10-29
申请号：US13314270
申请日：2011-12-08
申请人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
发明人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
IPC分类号： H01L21/302
CPC分类号： H01L27/11534 , H01L21/28273
摘要： Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.
摘要翻译：本文公开了在蚀刻工艺期间保护升高的多晶硅结构的各种方法。在一个示例中，该方法包括在用于存储器件的半导体衬底之上形成层堆叠，在存储器件的层堆叠之上形成保护掩模层，并执行至少一个蚀刻工艺以限定晶体管的栅电极，而保护罩位于存储器件的层堆叠之上。

5. 发明申请

US20130149851A1 Methods of Protecting Elevated Polysilicon Structures During Etching Processes 有权
标题翻译：在蚀刻过程中保护高架多晶硅结构的方法
公开(公告)号：US20130149851A1
公开(公告)日：2013-06-13
申请号：US13314270
申请日：2011-12-08
申请人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
发明人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
IPC分类号： H01L21/28
CPC分类号： H01L27/11534 , H01L21/28273
摘要： Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.
摘要翻译：本文公开了在蚀刻工艺期间保护升高的多晶硅结构的各种方法。在一个示例中，该方法包括在用于存储器件的半导体衬底之上形成层堆叠，在存储器件的层堆叠之上形成保护掩模层，并执行至少一个蚀刻工艺以限定晶体管的栅电极，而保护罩位于存储器件的层堆叠之上。

6. 发明授权

US08940637B2 Method for forming through silicon via with wafer backside protection 有权
标题翻译：通过硅晶片背面保护形成硅通孔的方法
公开(公告)号：US08940637B2
公开(公告)日：2015-01-27
申请号：US13542256
申请日：2012-07-05
申请人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L21/44 , H01L21/768 , H01L21/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
摘要翻译：具有贯通硅通孔（TSV）的半导体器件不形成铜污染。实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层，硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到暴露TSV底部的触点。

7. 发明授权

US08518775B2 Integration of eNVM, RMG, and HKMG modules 有权
标题翻译：集成eNVM，RMG和HKMG模块
公开(公告)号：US08518775B2
公开(公告)日：2013-08-27
申请号：US13251444
申请日：2011-10-03
申请人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
发明人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L21/823456 , H01L21/76229 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/11546 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.
摘要翻译：通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

8. 发明申请

US20130082318A1 INTEGRATION OF eNVM, RMG, AND HKMG MODULES 有权
标题翻译：整合eNVM，RMG和HKMG模块
公开(公告)号：US20130082318A1
公开(公告)日：2013-04-04
申请号：US13251444
申请日：2011-10-03
申请人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
发明人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
IPC分类号： H01L29/792 , H01L21/762
CPC分类号： H01L21/823456 , H01L21/76229 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/11546 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.
摘要翻译：通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

9. 发明申请

US20140008810A1 METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION 有权
标题翻译：通过硅片防止背面保护形成硅的方法
公开(公告)号：US20140008810A1
公开(公告)日：2014-01-09
申请号：US13542256
申请日：2012-07-05
申请人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L21/306 , H01L23/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
摘要翻译：具有贯通硅通孔（TSV）的半导体器件不形成铜污染。实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层，硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到暴露TSV底部的触点。

10. 发明授权

US08405222B2 Integrated circuit system with via and method of manufacture thereof 有权
标题翻译：集成电路系统及其制造方法
公开(公告)号：US08405222B2
公开(公告)日：2013-03-26
申请号：US12825266
申请日：2010-06-28
申请人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
发明人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L21/7684
摘要： A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer.
摘要翻译：集成电路系统的制造方法包括：在体基板上形成蚀刻停止层; 在所述蚀刻停止层上形成缓冲层; 在缓冲层上形成硬掩模; 通过所述蚀刻停止层形成穿透硅通孔，所述硬掩模被检测并且所述缓冲层以低的下压力去除; 以及在穿通硅通孔和蚀刻停止层上形成钝化层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式