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1. 发明授权

US5872063A Self-aligned contact structures using high selectivity etching 失效
标题翻译：使用高选择性蚀刻的自对准接触结构
公开(公告)号：US5872063A
公开(公告)日：1999-02-16
申请号：US5568
申请日：1998-01-12
申请人： Li-chih Chao , Jhon-Jhy Liaw , Yuan-Chang Huang , Jin-Yuan Lee
发明人： Li-chih Chao , Jhon-Jhy Liaw , Yuan-Chang Huang , Jin-Yuan Lee
IPC分类号： H01L21/311 , H01L21/60 , H01L21/70
CPC分类号： H01L21/76897 , H01L21/31116 , Y10S257/90
摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.
摘要翻译：描述了自对准结构和蚀刻自对准结构中的接触孔的方法。选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。氧化硅层沉积在蚀刻停止层上。使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率至少两个。

2. 发明授权

US06172411B2 Self-aligned contact structures using high selectivity etching 有权
标题翻译：使用高选择性蚀刻的自对准接触结构
公开(公告)号：US06172411B2
公开(公告)日：2001-01-09
申请号：US09208921
申请日：1998-12-10
申请人： Li-chih Chao , Jhon-Jhy Liaw , Yuan-Chang Huang , Jin-Yuan Lee
发明人： Li-chih Chao , Jhon-Jhy Liaw , Yuan-Chang Huang , Jin-Yuan Lee
IPC分类号： H01L27088
CPC分类号： H01L21/76897 , H01L21/31116 , Y10S257/90
摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.
摘要翻译：描述了自对准结构和蚀刻自对准结构中的接触孔的方法。选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。氧化硅层沉积在蚀刻停止层上。使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率至少两个。

3. 发明授权

US06184149B2 Method for monitoring self-aligned contact etching 失效
标题翻译：监测自对准接触蚀刻的方法
公开(公告)号：US06184149B2
公开(公告)日：2001-02-06
申请号：US08918315
申请日：1997-08-26
申请人： Li-Chih Chao , Yuan-Chang Huang
发明人： Li-Chih Chao , Yuan-Chang Huang
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31116 , H01L22/20
摘要： The present invention provides a method for monitoring a self-aligned contact (SAC) etching process. A wafer with an oxide layer serves as an oxide control wafer. The oxide layer is formed on the substrate. The oxide control wafer and a SAC wafer with SAC structure are simultaneously treated with a SAC etching process in an etching chamber with the same etching recipe. A contact hole is formed by etching the oxide layer of the oxide control wafer after the SAC etching process. The depth of a profile transition point and the depth of etching stop for the oxide control wafer can be observed by cross-section SEM. The profile transition depth in the oxide control wafer corresponds to the etching thickness of SiN corner loss in the SAC wafer. Therefore, the profile transition depth and the depth of etching stop in the oxide control wafer can be used to monitor the etching chamber condition.
摘要翻译：本发明提供一种用于监测自对准接触（SAC）蚀刻工艺的方法。具有氧化物层的晶片用作氧化物控制晶片。在基板上形成氧化物层。具有SAC结构的氧化物控制晶片和SAC晶片在蚀刻室中用SAC蚀刻工艺同时用相同的蚀刻配方进行处理。在SAC蚀刻工艺之后通过蚀刻氧化物控制晶片的氧化物层形成接触孔。通过横截面SEM可以观察到轮廓转变点的深度和氧化物控制晶片的蚀刻停止深度。氧化物控制晶片中的轮廓转移深度对应于SAC晶片中SiN角损失的蚀刻厚度。因此，可以使用氧化物控制晶片中的轮廓转移深度和蚀刻停止深度来监测蚀刻室状况。

4. 发明授权

US07744953B2 Method for forming self-cleaning coating comprising hydrophobically-modified particles 有权
标题翻译：用于形成包含疏水改性颗粒的自清洁涂层的方法
公开(公告)号：US07744953B2
公开(公告)日：2010-06-29
申请号：US11318566
申请日：2005-12-28
申请人： Yuan-Chang Huang , Yuung-Ching Sheen , Yih-Her Chang , Kuo-Feng Lo
发明人： Yuan-Chang Huang , Yuung-Ching Sheen , Yih-Her Chang , Kuo-Feng Lo
IPC分类号： B05D3/02
CPC分类号： B05D5/08 , Y10T428/2809
摘要： A method for forming self-cleaning coating comprising hydrophobically-modified particles. Micro- or nano-particles are treated with a hydrophobic agent and an additive to form larger particles with the hydrophobic agent and the additive bonded thereto. A binder or crosslinker is attached to the larger particles by forming chemical bonds with at least one of the additive, the hydrophobic agent, and the particles, thus forming a coating material capable of forming self-cleaning coating.
摘要翻译：一种形成包含疏水改性颗粒的自清洁涂层的方法。用疏水剂和添加剂处理微米或纳米颗粒以与疏水剂和添加剂结合的较大颗粒形成。通过与添加剂，疏水剂和颗粒中的至少一种形成化学键，粘合剂或交联剂附着到较大的颗粒上，从而形成能够形成自清洁涂层的涂料。

5. 发明申请

US20080081395A1 Wafer level package structure of optical-electronic device and method for making the same 失效
公开(公告)号：US20080081395A1
公开(公告)日：2008-04-03
申请号：US11984014
申请日：2007-11-13
申请人： Yuan-Chang Huang , Tai-Hung Chen , Yao-Sheng Lin , Su-Tsai Lu
发明人： Yuan-Chang Huang , Tai-Hung Chen , Yao-Sheng Lin , Su-Tsai Lu
IPC分类号： H01L31/18
CPC分类号： H01L27/14683 , H01L27/14618 , H01L27/14687 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/13 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.

6. 发明申请

US20080063797A1 Low stain and low mist adhesion coating 有权
标题翻译：低污染和低雾附着涂层
公开(公告)号：US20080063797A1
公开(公告)日：2008-03-13
申请号：US11976850
申请日：2007-10-29
申请人： Yuan-Chang Huang , Leng-Long Jou , Yuung-Ching Sheen , Yih-Her Chang , Chia-Lin Wen , Hsiao-Hua Wu
发明人： Yuan-Chang Huang , Leng-Long Jou , Yuung-Ching Sheen , Yih-Her Chang , Chia-Lin Wen , Hsiao-Hua Wu
IPC分类号： B05D5/12 , B05D1/12
CPC分类号： B05D5/08 , B08B17/06 , B08B17/065 , C04B41/009 , C04B41/4922 , Y10T428/31598 , C04B41/463 , C04B41/4853 , C04B41/4961 , C04B41/502 , C04B41/5072 , C04B33/00 , C04B28/182
摘要： A low stain and low mist adhesion coating. Micro- or nano-particles are treated with a hydrophobic agent and an additive to form larger microstructure with the hydrophobic agent and the additive bonded thereto forming a low stain and low mist adhesion coating material. A low stain and low mist adhesion coating formed from the material has a contact angle of at least 130°. In addition, the low stain and low mist adhesion coating has less than 60% mist adhesion area.
摘要翻译：低污染和低雾附着涂层。用疏水剂和添加剂处理微米或纳米颗粒以与疏水剂一起形成更大的微结构，并且结合到其上的添加剂形成低污点和低雾度粘附涂层材料。由该材料形成的低污渍和低雾附着涂层具有至少130°的接触角。此外，低污染和低雾度粘附涂层具有小于60％的雾粘附面积。

7. 发明授权

US07317235B2 Wafer level package structure of optical-electronic device and method for making the same 失效
标题翻译：光电子器件的晶圆级封装结构及其制造方法
公开(公告)号：US07317235B2
公开(公告)日：2008-01-08
申请号：US11082899
申请日：2005-03-18
申请人： Yuan-Chang Huang , Tai-Hung Chen , Yao-Sheng Lin , Su-Tsai Lu
发明人： Yuan-Chang Huang , Tai-Hung Chen , Yao-Sheng Lin , Su-Tsai Lu
IPC分类号： H01L31/0203
CPC分类号： H01L27/14683 , H01L27/14618 , H01L27/14687 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/13 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.
摘要翻译：公开了一种光电子器件的晶片级封装结构及其制造方法。光电子器件的晶片级封装结构通过采用其表面具有多个光敏区域并分成单个封装器件的衬底来提供。制造步骤首先涉及提供具有表面具有光敏区域和接合焊盘的几个芯片的基板，并且提供其表面具有导电电路和划线的透明层。然后，接合焊盘接合到导电电路，并且在芯片上形成保护层以暴露部分导电电路。在保护层上形成导电膜，并且导电膜与延伸的导电电路接触以形成光电子器件的晶片级封装结构。最后，根据划线对透明层进行切割，形成单独的封装装置。

8. 发明授权

US07154176B2 Conductive bumps with non-conductive juxtaposed sidewalls 有权
标题翻译：具有非导电并置侧壁的导电凸块
公开(公告)号：US07154176B2
公开(公告)日：2006-12-26
申请号：US10714277
申请日：2003-11-14
申请人： Yuan-Chang Huang , Shyh-Ming Chang , Su-Chia Lu
发明人： Yuan-Chang Huang , Shyh-Ming Chang , Su-Chia Lu
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/83 , H01L2224/05026 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/114 , H01L2224/116 , H01L2224/13099 , H01L2224/16 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2224/838 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/0781 , H01L2924/14 , H01L2924/3025 , H01L2224/05099
摘要： A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.
摘要翻译：一种微电子结构，其具有多个导电凸块的基板，用于在倒装芯片电子组件的制造中与电子基板上的接合焊盘接触。每个导电凸块包括导体层，该导电层不存在于凸起的至少一个侧壁中，以防止电子组件中相邻的导电凸块之间的短路电路无意形成。

9. 发明申请

US20060147829A1 Method for forming coating material and the material formed thereby 有权
标题翻译：用于形成涂层材料的方法及由此形成的材料
公开(公告)号：US20060147829A1
公开(公告)日：2006-07-06
申请号：US11318459
申请日：2005-12-28
申请人： Yuan-Chang Huang , Yuung-Ching Sheen , Yih-Her Chang , Kuo-Feng Lo
发明人： Yuan-Chang Huang , Yuung-Ching Sheen , Yih-Her Chang , Kuo-Feng Lo
IPC分类号： G03G9/00 , C09C1/36
CPC分类号： C09D7/69 , C08K3/36 , C08K9/02 , C08K9/04 , C08K9/06 , C09D7/61 , C09D7/67 , C09D7/68
摘要： A method for forming a coating material capable of forming a hydrophobic, microstructured surface. The method comprises treating micro or nano-particles particles with a hydrophobic agent and an additive to form larger particles with the hydrophobic agent bonded thereto. The invention also comprises the coating material thus formed.
摘要翻译：一种形成能形成疏水，微结构化表面的涂层材料的方法。该方法包括用疏水剂和添加剂处理微粒或纳米颗粒以形成与疏水剂结合的更大颗粒。本发明还包括如此形成的涂料。

10. 发明授权

US06211083B1 Use of a novel capped anneal procedure to improve salicide formation 有权
标题翻译：使用新型封端退火方法来改善自杀化合物的形成
公开(公告)号：US06211083B1
公开(公告)日：2001-04-03
申请号：US09550263
申请日：2000-04-17
申请人： Jiunn-Der Yang , Chaucer Chung , Yuan-Chang Huang
发明人： Jiunn-Der Yang , Chaucer Chung , Yuan-Chang Huang
IPC分类号： H01L214763
CPC分类号： H01L29/665 , H01L21/28518
摘要： A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.
摘要翻译：已经开发了在MOSFET器件的区域上形成低电阻二硅化钛层的工艺。该方法的特征在于在第一相，高电阻，二硅化钛区域上沉积封盖的氧化硅层。封装，氧化硅层具有压缩应力，降低了形成有拉伸应力的二硅化钛区域从MOSFET器件的下面区域的粘附损失或剥离的风险，例如从狭窄的顶部表面宽度，多晶硅栅结构。此外，封盖氧化硅层保护下游的二硅化钛区域与用于将第一相，高电阻，二硅化钛区域转化为第二相，低电阻，二硅化钛区域的退火循环期间使用的环境。

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