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1. 发明申请

US20060058984A1 Device for parallel data processing as well as a camera system comprising such a device 失效
标题翻译：用于并行数据处理的装置以及包括这种装置的相机系统
公开(公告)号：US20060058984A1
公开(公告)日：2006-03-16
申请号：US10534476
申请日：2003-11-06
申请人： Leonardus Sevat , Richard Kleihorst , Andre Nieuwland
发明人： Leonardus Sevat , Richard Kleihorst , Andre Nieuwland
IPC分类号： G06F15/00
CPC分类号： H04N5/335
摘要： The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix (100) in which processors (103) are arranged in rows (101) and columns (102). Furthermore, the device (100) comprises first and second external data ports (107, 108). The rows (101) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors (103) have a first processor data port (104), which is connected with one of the first external data ports (107) by means of first essentially straight connection. The processors (103) further comprise a second processor data port (105), which is connected with one of the second external data ports (108) by means of an essentially straight second connection (110). The first connection (107) and the second connection (108) are oriented substantially orthogonal to each other. A problem associated with conventional DSPs is that the connections to and from the processors within the DSP take up large amounts of silicon area. By arranging both rows and columns of the DSP according to the invention in a stepwise manner the connections may be essentially straight, thus minimizing their lengths and thus the surface area occupied.
摘要翻译：本发明涉及一种用于并行数据处理的设备，一种DSP。根据本发明的装置包括处理器矩阵（100），其中处理器（103）被布置成行（101）和列（102）。此外，设备（100）包括第一和第二外部数据端口（107,108）。行（101）以逐步的方式布置并且列以逐步的方式布置。处理器（103）具有第一处理器数据端口（104），其通过第一基本上直的连接与第一外部数据端口（107）中的一个连接。处理器（103）还包括第二处理器数据端口（105），其通过基本上直的第二连接（110）与第二外部数据端口（108）之一连接。第一连接（107）和第二连接（108）彼此基本正交。与常规DSP相关的一个问题是与DSP内部的处理器的连接占用大量的硅面积。通过按照本发明以逐步的方式布置DSP的行和列，连接可以是基本上直的，从而使其长度最小化并因此使占用的表面积最小化。

2. 发明申请

US20060214820A1 Decoder circuit 审中-公开
标题翻译：解码电路
公开(公告)号：US20060214820A1
公开(公告)日：2006-09-28
申请号：US10567691
申请日：2004-08-05
申请人： Richard Kleihorst , Victor Emmanuel Van Dijk , Andre Nieuwland
发明人： Richard Kleihorst , Victor Emmanuel Van Dijk , Andre Nieuwland
IPC分类号： H03M7/00
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： A decoder circuit, for example a dual-rail decoder, receives input signals (43) from the end of a communications bus (not shown). The parity is calculated over the data wires (Do, D1, D2, D3) using exclusive OR gates (45, 47, and 49). The calculated data parity signal (51) is compared with a transmitted parity signal (53) (shown as “carry”) in an exclusive OR gate (55). Rather than connecting the control signal (57) from the exclusive OR gate (55) directly to the multiplexers (590, 591, 592, 593), the control signal (57) is instead connected to a gating circuit (71). The gating circuit (71), for example a AND gate, receives the control signal (57) as a first input signal. The gating circuit (71) also receives a second input signal in the form of a gating control signal (73). The gating control signal (73) is delayed by a predetermined amount, for example corresponding to the worst case delay of the signals in the input data signals (43). Thus, the gating control signal (73) does not control the gating circuit until such time as all of the data signals are valid, ie until the last transition on the data signal (43) has occurred, thereby preventing glitches and reducing power consumption in the decoder circuit.
摘要翻译：解码器电路，例如双轨解码器，从通信总线（未示出）的末端接收输入信号（43）。通过数据线（D SUB，D 1，D 2，D 3 3）计算奇偶校验，使用异或门（45,47和49）。将计算出的数据奇偶校验信号（51）与异或门（55）中的发送奇偶校验信号（53）（示为“进位”）进行比较。不是将控制信号（57）从异或门（55）直接连接到多路复用器（590,591,592,593），而是将控制信号（57）连接到门控电路（71）。选通电路（71）（例如与门）接收控制信号（57）作为第一输入信号。选通电路（71）还接收门控控制信号（73）形式的第二输入信号。选通控制信号（73）被延迟预定量，例如对应于输入数据信号（43）中的信号的最差情况延迟。因此，选通控制信号（73）不控制门控电路，直到所有数据信号有效，即直到数据信号（43）上的最后一个转换发生为止，从而防止了毛刺和降低功耗解码电路。

3. 发明申请

US20050177588A1 Data communication bus 审中-公开
标题翻译：数据通信总线
公开(公告)号：US20050177588A1
公开(公告)日：2005-08-11
申请号：US10511513
申请日：2003-04-01
申请人： Danielle Rossi , Richard Kleihorst , Andre Nieuwland , Victor Emmanuel Van Dijk
发明人： Danielle Rossi , Richard Kleihorst , Andre Nieuwland , Victor Emmanuel Van Dijk
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L31/00 , H03M13/47 , H04L25/02 , H04L25/03 , H04L25/49 , G06F17/00
CPC分类号： H04L25/49
摘要： An electronic device has a data communication bus (200) mounted on a semiconductor substrate (120). The data communication bus (200) has a first conductor (102), a second conductor (104), a third conductor (106) and a fourth conductor (108). The conductors have been reordered and the distances (I1, I2, I3) between two neighboring conductors have been recalculated on the basis of the correlation between the data-bits conveyed by the conductors of the data communication bus (200), e.g. the number of times that the two transitions on two conductors have a predetermined value out of the total number of transitions on that conductor pair. Consequently, a data communication bus (200) is obtained in which the power consumption resulting from the charging of the cross-coupling capacitance between two neighboring conductors is reduced.
摘要翻译：电子设备具有安装在半导体衬底（120）上的数据通信总线（200）。数据通信总线（200）具有第一导体（102），第二导体（104），第三导体（106）和第四导体（108）。导体已经被重新排序，并且两个相邻导体之间的距离（I 1> 1，I 2，I 3 3）已经基于由数据通信总线（200）的导体传送的数据位之间的相关性，例如在两个导体上的两个跃迁的次数在该导体对上的总转换次数中具有预定值。因此，获得数据通信总线（200），其中由两个相邻导体之间的交叉耦合电容充电所产生的功耗减小。

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