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1. 发明授权

US6098168A System for completing instruction out-of-order which performs target address comparisons prior to dispatch 失效
标题翻译：用于完成在发送前执行目标地址比较的无序指令的系统
公开(公告)号：US6098168A
公开(公告)日：2000-08-01
申请号：US46867
申请日：1998-03-24
申请人： Lee Evan Eisen , Michael Putrino
发明人： Lee Evan Eisen , Michael Putrino
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A mechanism structured to check for instruction collisions at the Dispatch Unit rather than the Completion Unit. In processors which issue multiple commands simultaneously, a flag bit is sent to the Completion Unit and attached to the instruction in the queue that follows the other in program order if they both have the same targeted address. When the instructions from position 1 and position 2 of the instruction queue are ready to issue, the Completion Unit checks position 2 for a flag bit. If there is a bit, then the instruction in position 1 is discarded and the instruction in position 2 is written to the target address. If there is no flag bit with the instruction in position 2, the instruction in position 1 is written to the target register. This method eliminates the need to compare all the targeted addresses that are associated with the rename registers. It requires two comparisons instead of a minimum of 15 comparisons.
摘要翻译：一种结构化的检查在调度单位而不是完成单位的指令冲突的机制。在同时发出多个命令的处理器中，如果标志位都具有相同的目标地址，则将标志位发送到完成单元并附加到队列中的跟随另一命令的指令。当指令队列的位置1和位置2的指令准备发出时，完成单元检查位置2是否有一个标志位。如果有位，则丢弃位置1的指令，将位置2中的指令写入目标地址。如果位置2中的指令没有标志位，则将位置1的指令写入目标寄存器。该方法不需要比较与重命名寄存器相关的所有目标地址。它需要两次比较，而不是至少15次比较。

2. 发明授权

US07254693B2 Selectively prohibiting speculative execution of conditional branch type based on instruction bit 失效
标题翻译：选择性地禁止基于指令位的推测性执行条件分支类型
公开(公告)号：US07254693B2
公开(公告)日：2007-08-07
申请号：US11002522
申请日：2004-12-02
申请人： Lee Evan Eisen , Francis Patrick O'Connell
发明人： Lee Evan Eisen , Francis Patrick O'Connell
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/30058 , G06F9/30181 , G06F9/3844 , G06F9/3851 , G06F9/3867
摘要： A method, apparatus, and computer program product are disclosed for selectively prohibiting speculative conditional branch execution. A particular type of conditional branch instruction is selected. An indication is stored within each instruction that is the particular type of conditional branch instruction. A processor then fetches a first instruction from code that is to be executed. A determination is made regarding whether the first instruction includes the indication. In response to determining that the instruction includes the indication: speculative execution of the first instruction is prohibited, an actual location to which the first instruction will branch is resolved, and execution of the code is branched to the actual location. In response to determining that the instruction does not include the indication, the first instruction is speculatively executed.
摘要翻译：公开了用于选择性地禁止推测性条件分支执行的方法，装置和计算机程序产品。选择特定类型的条件分支指令。指示存储在作为条件分支指令的特定类型的每个指令内。然后处理器从要执行的代码中获取第一条指令。确定第一指令是否包括指示。响应于确定指令包括指示：禁止第一指令的推测执行，第一指令将分支的实际位置被解析，并且代码的执行被分支到实际位置。响应于确定指令不包括指示，推测性地执行第一指令。

3. 发明授权

US07904697B2 Load register instruction short circuiting method 有权
标题翻译：加载寄存器指令短路方式
公开(公告)号：US07904697B2
公开(公告)日：2011-03-08
申请号：US12044013
申请日：2008-03-07
申请人： Brian David Barrick , Brian William Curran , Lee Evan Eisen
发明人： Brian David Barrick , Brian William Curran , Lee Evan Eisen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30032 , G06F9/384
摘要： An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.
摘要翻译：一种用于执行加载寄存器指令的装置和方法，其中将负载寄存器指令的源数据保留在其原始物理寄存器中，同时将架构化目标寄存器映射到同一物理目标寄存器。在这种状态下，两个架构的寄存器对一个物理寄存器进行了别名。当加载地址指令的源寄存器被指定为后续指令的目标地址时，将自由物理寄存器分配给加载寄存器源寄存器。并且通过这个任务，别名被破坏了。类似地，当加载地址指令的目标寄存器是后续指令的目标地址时，新的物理寄存器被分配给加载寄存器目标地址。并且通过这个任务，别名被破坏了。

4. 发明申请

US20090228692A1 Load Register Instruction Short Circuiting Method 有权
标题翻译：加载寄存器指令短路方法
公开(公告)号：US20090228692A1
公开(公告)日：2009-09-10
申请号：US12044013
申请日：2008-03-07
申请人： Brian David Barrick , Brian William Curran , Lee Evan Eisen
发明人： Brian David Barrick , Brian William Curran , Lee Evan Eisen
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/384
摘要： An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.
摘要翻译：一种用于执行加载寄存器指令的装置和方法，其中将负载寄存器指令的源数据保留在其原始物理寄存器中，同时将架构化目标寄存器映射到同一物理目标寄存器。在这种状态下，两个架构的寄存器对一个物理寄存器进行了别名。当加载地址指令的源寄存器被指定为后续指令的目标地址时，将自由物理寄存器分配给加载寄存器源寄存器。并且通过这个任务，别名被破坏了。类似地，当加载地址指令的目标寄存器是后续指令的目标地址时，新的物理寄存器被分配给加载寄存器目标地址。并且通过这个任务，别名被破坏了。

5. 发明授权

US06430678B1 Scoreboard mechanism for serialized string operations utilizing the XER 失效
标题翻译：使用XER的串行字符串操作的记分板机制
公开(公告)号：US06430678B1
公开(公告)日：2002-08-06
申请号：US09363463
申请日：1999-07-29
申请人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
发明人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
IPC分类号： G06F930
CPC分类号： G06F9/30018 , G06F9/3017 , G06F9/325 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.
摘要翻译：通过使用指令排序器单元记分板提供XER记分板功能。如果XER由前一条指令使用，记分板位将被置位。如果获取使用XER的新指令，则生成对XER的虚拟读取以测试记分板位以确定记分板位是否设置。如果执行虚拟读取时记分板位未设置，则X形式的字符串将继续执行。如果在执行虚拟机时设置了记分板位，则流水线停止，直到记分板位被清除，然后执行填充有生成的填充IOP（虚拟或NOP）的X形式字符串。执行访问指令后，记分板位被清除。

6. 发明授权

US06321380B1 Method and apparatus for modifying instruction operations in a processor 有权
标题翻译：用于修改处理器中的指令操作的方法和装置
公开(公告)号：US06321380B1
公开(公告)日：2001-11-20
申请号：US09345161
申请日：1999-06-29
申请人： John Edward Derrick , Lee Evan Eisen , Kevin Franklin Reick
发明人： John Edward Derrick , Lee Evan Eisen , Kevin Franklin Reick
IPC分类号： G06F1212
CPC分类号： G06F9/3017 , G06F9/268 , G06F9/328
摘要： A “soft-patch” allows an instruction or group of instructions to be replaced with a pre-loaded instruction or group of instructions. When an Instruction Fetch Unit (IFU) fetches an instruction, the instruction is sent through a Compare and Mask (CAM) circuit which masks and compares, in parallel, the instruction with up to eight pre-defined masks and values. The masks and values are pre-loaded by a service processor to CAM circuits which are located in an Instruction Dispatch Unit (IDU) and the IFU in the central processor. An instruction that is deemed a match, is tagged by the IFU as a “soft-microcode” instruction. When the IDU receives the soft-microcode instruction for decoding, it detects the soft microcode marking and sends the marked instruction to a soft-microcode unit; a separate parallel pipeline in the IDU. The soft-microcode unit then sends the instruction through a CAM circuit which returns an index (or address) for RAM. The index is used to read values out of IDU RAM and generate replacement instructions. Additionally, an Internal Operation that will cause the processor core to perform an unconditional branch to a fixed real address, can be loaded into the IDU RAM allowing an instruction to be replaced by a subroutine or handler routine contained outside the processor core.
摘要翻译： “软补丁”允许用预加载指令或指令组替换指令或指令组。当指令获取单元（IFU）取指令时，该指令通过比较和掩码（CAM）电路发送，该电路将指令与多达八个预定义的掩码和值并行进行掩蔽和比较。掩码和值由服务处理器预加载到位于指令调度单元（IDU）中的CAM电路和中央处理器中的IFU。被认为是匹配的指令被IFU标记为“软微码”指令。当IDU接收到用于解码的软微码指令时，它检测软微码标记，并将标记的指令发送到软微码单元; 在IDU中单独的并行管道。软微码单元然后通过CAM电路发送指令，CAM电路返回RAM的索引（或地址）。该索引用于读取IDU RAM中的值，并生成替换指令。此外，将使处理器内核对固定的实际地址执行无条件分支的内部操作可以被加载到IDU RAM中，从而允许由包含在处理器核心外部的子程序或处理程序例程替换指令。

7. 发明授权

US06442675B1 Compressed string and multiple generation engine 失效
标题翻译：压缩字符串和多代引擎
公开(公告)号：US06442675B1
公开(公告)日：2002-08-27
申请号：US09363464
申请日：1999-07-29
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le
IPC分类号： G06F938
CPC分类号： G06F9/30043 , G06F9/3017
摘要： A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the operations contained in the string instruction. The operations that make up the string instruction are routed to parallel functional units and executed. The state-machine manipulates the size of the operations in the string instruction and whether or not the instructions need to be generated.
摘要翻译：提供通用的可编程数据流状态机以接收关于特定字符串指令的信息。字符串指令被解析为字符串指令中包含的所有操作。构成字符串指令的操作被路由到并行功能单元并执行。状态机在字符串指令中操作操作的大小以及是否需要生成指令。

8. 发明授权

US07890738B2 Method and logical apparatus for managing processing system resource use for speculative execution 失效
标题翻译：用于管理用于投机执行的处理系统资源使用的方法和逻辑装置
公开(公告)号：US07890738B2
公开(公告)日：2011-02-15
申请号：US11039498
申请日：2005-01-20
申请人： Lee Evan Eisen , David Stephen Levitan , Francis Patrick O'Connell , Wolfram M. Sauer
发明人： Lee Evan Eisen , David Stephen Levitan , Francis Patrick O'Connell , Wolfram M. Sauer
IPC分类号： G06F9/50 , G06F9/42
CPC分类号： G06F9/5011 , G06F9/3844 , G06F9/3851 , G06F2209/507 , Y02D10/22
摘要： A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is low. The resource control applied may be the number of instruction fetches allocated to the thread or the number of execution time slices. Alternatively, or in combination, the size of a prefetch instruction storage allocated to the thread may be limited. The control condition may be comparison of the number of correct or incorrect speculations to a threshold, comparison of the number of correct to incorrect speculations, or a more complex evaluator such as the size of a ratio of incorrect to total speculations.
摘要翻译：用于管理用于推测性执行的处理系统资源使用的方法和逻辑装置降低与程序指令的无效推测执行相关联的功率和性能负担。投机执行效率的度量用于减少分配给线程的资源，同时投机效率低。应用的资源控制可以是分配给线程的指令获取的数量或执行时间片的数量。或者或组合地，分配给线程的预取指令存储器的大小可能受到限制。控制条件可以是正确的或不正确的猜测的数量与阈值的比较，正确到不正确的猜测的数量的比较，或比较复杂的评估者，比如不正确比例与总猜测的比例。

9. 发明授权

US07194645B2 Method and apparatus for autonomic policy-based thermal management in a data processing system 失效
标题翻译：数据处理系统中基于自治策略的热管理方法和装置
公开(公告)号：US07194645B2
公开(公告)日：2007-03-20
申请号：US11054261
申请日：2005-02-09
申请人： Andreas Bieswanger , Lee Evan Eisen , James Stephen Fields, Jr. , Michael Stephen Floyd , Bradley David McCredie , Naresh Nayar
发明人： Andreas Bieswanger , Lee Evan Eisen , James Stephen Fields, Jr. , Michael Stephen Floyd , Bradley David McCredie , Naresh Nayar
IPC分类号： G06F1/26 , G01K1/08 , G01K17/00 , G05B11/00 , G05B13/00 , G05D23/00 , G05B9/00 , G06F11/00 , G06F1/20 , H05K7/20
CPC分类号： G06F1/206
摘要： A method, apparatus and computer instructions are provided to autonomically monitor and adjust system characteristics based on a customer optimization goal specified in a policy or profile. An autonomic management component is implemented in firmware comprising a set of control algorithms. Response to reading system characteristics from a plurality of sensors, the autononmic management component selects at least one control algorithm from the set and the control algorithm adjusts the parameters of the system characteristic to optimize performance according to the optimization goal specified by the customer.
摘要翻译：提供了一种方法，装置和计算机指令，用于基于在策略或简档中指定的客户优化目标自主地监视和调整系统特征。在包括一组控制算法的固件中实现自主管理组件。响应于多个传感器的读取系统特性，自动管理部件从集合中选择至少一个控制算法，并且控制算法根据客户指定的优化目标调整系统特性的参数以优化性能。

10. 发明授权

US06385719B1 Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中同步并行管线的方法和装置
公开(公告)号：US06385719B1
公开(公告)日：2002-05-07
申请号：US09345719
申请日：1999-06-30
申请人： John Edward Derrick , Brian R. Konigsburg , Lee Evan Eisen , David Stephen Levitan
发明人： John Edward Derrick , Brian R. Konigsburg , Lee Evan Eisen , David Stephen Levitan
IPC分类号： G06F938
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the branch pipeline are assigned a concatenated version (group tag concatenated with instruction lane) of the transfer tag which is used to match on requests to flush any newer instructions. All potential instruction or Internal Operation latches in the decode pipeline must perform a match and if a match is encountered, all valid bits associated with newer instructions or internal operations upstream from the match are cleared. The transfer tag representing the next instruction to be processed in the branch pipeline is passed to the Instruction Dispatch Unit. The Instruction Dispatch Unit queries the branch pipeline to compare its transfer tag with transfer tags of instructions in the branch pipeline. If the transfer tag matches a branch instruction tag the Instruction Decode Unit is stalled until the branch instruction is processed thus, providing a synchronizing method for the parallel pipelines.
摘要翻译：传送标签由指令提取单元生成，并在指令流水线中传送给解码单元，每个指令组由读取器在分支预测期间取出。为分支流水线提取的组中的单独指令被分配用于匹配在刷新任何较新指令的请求上的传送标签的级联版本（组标签与指令通道连接）。解码流水线中的所有潜在指令或内部操作锁存器必须执行匹配，并且如果遇到匹配，将清除与较新指令相关联的所有有效位或匹配上游的内部操作。表示在分支管线中要处理的下一条指令的传送标签被传递到指令调度单元。指令调度单元查询分支流水线以将其传输标签与分支流水线中的指令的传输标签进行比较。如果转移标签与分支指令标签匹配，则指令解码单元停止，直到处理分支指令为止，为并行管线提供同步方法。

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