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1. 发明授权

US5852582A Non-volatile storage device refresh time detector 失效
标题翻译：非易失性存储设备刷新时间检测器
公开(公告)号：US5852582A
公开(公告)日：1998-12-22
申请号：US801305
申请日：1997-02-18
申请人： Lee E. Cleveland , Yuan Tang , Jonathan Su , Chi Chang , Chung K. Chang
发明人： Lee E. Cleveland , Yuan Tang , Jonathan Su , Chi Chang , Chung K. Chang
IPC分类号： G11C16/28 , G11C16/32 , G11C16/34 , G11C13/00
CPC分类号： G11C16/3431 , G11C16/28 , G11C16/32 , G11C16/3418
摘要： A timing apparatus for monitoring when a memory array in a non-volatile storage device needs to be refreshed includes a programmable semiconductor device and detecting means for detecting when the amount of charge on the programmable semiconductor device has diminished to at most a threshold amount. In one embodiment, the programmable semiconductor device is a floating gate transistor programmed by adding charge to the floating gate. The detecting means monitors the I.sub.DS current of the transistor and determines an array refresh time when more than a negligible amount of I.sub.DS current is detected.
摘要翻译：用于监视非易失性存储装置中的存储器阵列何时需要刷新的定时装置包括可编程半导体器件和检测装置，用于检测可编程半导体器件上的电荷量何时已降至至多阈值量。在一个实施例中，可编程半导体器件是通过向浮动栅极增加电荷而编程的浮栅晶体管。检测装置监视晶体管的IDS电流，并且当检测到多于可忽略的IDS电流量时，确定阵列刷新时间。

2. 发明授权

US5485423A Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS 失效
标题翻译：消除5伏隧道氧化物中循环诱导电子捕获的方法，只有闪存EEPROMS
公开(公告)号：US5485423A
公开(公告)日：1996-01-16
申请号：US320368
申请日：1994-10-11
申请人： Yuan Tang , Chi Chang , Michael A. Van Buskirk , Chung K. Chang
发明人： Yuan Tang , Chi Chang , Michael A. Van Buskirk , Chung K. Chang
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
摘要翻译：提供了一种用于消除快速EEPROM装置的隧道氧化物中的循环诱导电子捕获的改进方法。在整个擦除周期期间，相对较低的正脉冲电压被施加到EEPROM器件的源极区域。同时，在整个擦除周期期间，向EEPROM器件的控制栅极施加负斜坡电压，从而实现从擦除周期开始到擦除周期结束的平均隧道场。

3. 发明授权

US06961267B1 Method and device for programming cells in a memory array in a narrow distribution 有权
标题翻译：用于以窄分布编程存储器阵列中的单元的方法和装置
公开(公告)号：US06961267B1
公开(公告)日：2005-11-01
申请号：US10738301
申请日：2003-12-16
申请人： Richard M. Fastow , Lee E. Cleveland , Chi Chang
发明人： Richard M. Fastow , Lee E. Cleveland , Chi Chang
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/3468
摘要： Accurately programming a memory cell. A voltage is applied to a drain of the memory cell to program the cell. After applying the voltage, the cell is verified as to whether it is programmed to a desired level. The magnitude of the programming voltage is increased and applied to the drain, and the memory cell is re-verified for the desired level. This is repeated until the memory cell is programmed to the desired level. Additional memory cells are programmed in this fashion in order to program multiple memory cells in a narrow distribution around the desired level. The programming can be done one memory cell at a time or many cells can be programmed in parallel. Further a ramped programming voltage can applied to the gate of the memory cell(s), such that the ramped voltage to the gate and the ramped voltage to the drain both program the memory cell.
摘要翻译：准确编程存储单元。将电压施加到存储器单元的漏极以对单元进行编程。在施加电压之后，验证单元是否被编程到所需的电平。编程电压的大小被增加并施加到漏极，并且存储器单元被重新验证所需的电平。直到将存储单元编程到所需的电平为止。以这种方式对附加存储器单元进行编程，以便以围绕期望水平的窄分布来编程多个存储器单元。编程可以一次完成一个存储单元，或者可以并行编程多个单元。此外，斜坡编程电压可以施加到存储器单元的栅极，使得到栅极的斜坡电压和到漏极的斜坡电压都对存储器单元进行编程。

4. 发明授权

US06252803B1 Automatic program disturb with intelligent soft programming for flash cells 有权
标题翻译：自动程序干扰与闪存单元的智能软编程
公开(公告)号：US06252803B1
公开(公告)日：2001-06-26
申请号：US09692881
申请日：2000-10-23
申请人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
发明人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
IPC分类号： G11C1616
CPC分类号： G11C16/16
摘要： A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.
摘要翻译：提供擦除闪存电可擦除可编程只读存储器（EEPROM）设备的方法，其包括多个存储器单元。擦除脉冲被施加到多个存储单元。多个存储器单元被过度验证，并且过高修正脉冲被施加到被过度存储的存储单元附着的位线。重复此循环，直到所有的单元格都被验证为不被过高。多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则另一个擦除脉冲被施加到存储器单元。重复此循环，直到所有单元格都被验证为不被忽略。在擦除验证完成之后，多个存储器单元被软件程序验证，并且将软编程脉冲施加到具有低于预定义最小值的阈值电压的多个存储单元中的那些存储单元。重复该循环，直到具有低于预定义最小值的阈值电压的多个存储器单元中的所有那些存储器单元高于预定义的最小值。当多个存储单元中没有存储单元的阈值电压低于预先定义的最小值时，擦除方法被认为是完成的。

5. 发明授权

US5629893A System for constant field erasure in a flash EPROM 失效
标题翻译：闪存EPROM中的常量字段擦除系统
公开(公告)号：US5629893A
公开(公告)日：1997-05-13
申请号：US634512
申请日：1996-04-18
申请人： Yuan Tang , Chi Chang , James C. Yu
发明人： Yuan Tang , Chi Chang , James C. Yu
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.
摘要翻译：公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。在这样做时，可以以最小的压力擦除FLASH EPROM单元。此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

6. 发明授权

US5805502A System for constant field erasure in a FLASH EPROM 失效
标题翻译： FLASH EPROM中常量字段擦除的系统
公开(公告)号：US5805502A
公开(公告)日：1998-09-08
申请号：US795024
申请日：1997-02-04
申请人： Yuan Tang , Chi Chang , James C. Yu
发明人： Yuan Tang , Chi Chang , James C. Yu
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.
摘要翻译：公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。在这样做时，可以以最小的压力擦除FLASH EPROM单元。此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

7. 发明授权

US5596531A Method for decreasing the discharge time of a flash EPROM cell 失效
标题翻译：降低闪速EPROM单元的放电时间的方法
公开(公告)号：US5596531A
公开(公告)日：1997-01-21
申请号：US450167
申请日：1995-05-25
申请人： David K. Y. Liu , Ming S. Kwan , Chi Chang , Sameer Haddad , Yuan Tang
发明人： David K. Y. Liu , Ming S. Kwan , Chi Chang , Sameer Haddad , Yuan Tang
IPC分类号： G11C16/14 , G11C7/00
CPC分类号： G11C16/14
摘要： The present invention presents methods for reducing the discharge time of a Flash EPROM cell. In one aspect, a method includes the steps of forcing an ultraviolet voltage threshold, UVV.sub.t, below a discharge threshold voltage, V.sub.t. The method further comprises reducing the UVV.sub.t to about 0 V. Further, the method further comprises the step of reducing a core cell implant of a p-type dopant into a substrate of the cell. In a further aspect, a method for decreasing the discharge time includes the steps of providing a core cell implant of a p-type dopant into a surface of a substrate of the cell, and providing a surface doping of an n-type dopant into the core of the substrate, where the core implant reduces punchthrough and the surface doping of an n-type dopant reduces V.sub.t in the cell. In yet another aspect, a method for decreasing a discharge time of a Flash EPROM cell while reducing punchthrough includes the steps of providing a high energy core cell implant of a p type dopant into a substrate of the cell, wherein the core has a doping concentration profile with a low dopant concentration at a surface of the core to reduce UVV.sub.t and a high dopant concentration at lower than the surface to reduce punchthrough.
摘要翻译：本发明提出了减少闪存EPROM单元的放电时间的方法。在一个方面，一种方法包括以下步骤：将紫外线电压阈值UVVt强制在放电阈值电压Vt以下，该方法还包括将UVVt降低到约0V。此外，该方法还包括如下步骤：将p型掺杂剂细胞注入细胞的底物。在另一方面，一种减少放电时间的方法包括以下步骤：将p型掺杂剂的核心单元注入提供到电池的衬底的表面中，并且向n型掺杂剂表面掺杂衬底的芯部，其中芯体植入物减少穿透并且n型掺杂剂的表面掺杂减小了电池中的Vt。在另一方面，一种减少穿透时减少闪存EPROM单元的放电时间的方法包括以下步骤：将ap型掺杂剂的高能核心单元注入提供到电池的衬底中，其中芯具有掺杂浓度分布在芯的表面处具有低掺杂剂浓度以降低UVVt，并且在低于表面的情况下具有高掺杂剂浓度以减少穿透。

8. 发明授权

US09106734B2 Computer system and processor having integrated phone functionality 有权
标题翻译：具有集成手机功能的计算机系统和处理器
公开(公告)号：US09106734B2
公开(公告)日：2015-08-11
申请号：US13584527
申请日：2012-08-13
申请人： Chi Chang
发明人： Chi Chang
IPC分类号： H04M11/00 , H04M1/247 , G06F3/02 , G06F3/023 , G06F3/0489
CPC分类号： H04M1/2473 , G06F3/021 , G06F3/023 , G06F3/0489
摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.
摘要翻译：包括电话功能的计算机系统。计算机系统包括第一键盘和第一显示器。计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。计算机系统可以在第一模式，第二模式或第三模式中操作。在第一模式中，只有电话部分被激活，并且电话部分提供放置和接收电话呼叫的功能，而不从计算机系统移除。在第二模式中，处理器的电话部分和第一功能单元被激活。在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

9. 发明授权

US08455268B2 Gate replacement with top oxide regrowth for the top oxide improvement 有权
标题翻译：门顶置换，顶部氧化物再生长，用于顶部氧化物改良
公开(公告)号：US08455268B2
公开(公告)日：2013-06-04
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

10. 发明授权

US07915123B1 Dual charge storage node memory device and methods for fabricating such device 有权
标题翻译：双电荷存储节点存储器件及其制造方法
公开(公告)号：US07915123B1
公开(公告)日：2011-03-29
申请号：US11408866
申请日：2006-04-20
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Kyunghoon Min , Chi Chang
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Kyunghoon Min , Chi Chang
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792 , Y10S438/954
摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.
摘要翻译：提供了一种双节点存储器件及其制造方法。在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

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