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1. 发明申请

US20130189825A1 METHOD OF PRODUCING INSULATION TRENCHES IN A SEMICONDUCTOR ON INSULATOR SUBSTRATE 有权
标题翻译：在绝缘体基板上的半导体中生产绝缘栅的方法
公开(公告)号：US20130189825A1
公开(公告)日：2013-07-25
申请号：US13555356
申请日：2012-07-23
申请人： Yannick LE TIEC , Laurent GRENOUILLET , Maud VINET
发明人： Yannick LE TIEC , Laurent GRENOUILLET , Maud VINET
IPC分类号： H01L21/76
CPC分类号： H01L21/76 , H01L21/31111 , H01L21/31155 , H01L21/76237 , H01L21/76283
摘要： A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.
摘要翻译：一种在包括由半导体支撑层形成的绝缘体上半导体基板的基板和搁置在所述绝缘层上的绝缘层和置于所述绝缘层上的半导电层的器件中制造一个或多个沟槽的方法，所述方法包括以下步骤：：a）通过位于精细半导体层上的掩模层中的开口局部掺杂所述绝缘层的给定部分，b）选择性地去除所述开口底部的所述给定掺杂区域。

2. 发明申请

US20120256262A1 FIELD EFFECT TRANSISTOR WITH OFFSET COUNTER-ELECTRODE CONTACT 有权
标题翻译：具有偏移计数器电极接触的场效应晶体管
公开(公告)号：US20120256262A1
公开(公告)日：2012-10-11
申请号：US13439356
申请日：2012-04-04
申请人： Maud VINET , Laurent GRENOUILLET , Yannick LE TIEC , Nicolas POSSEME
发明人： Maud VINET , Laurent GRENOUILLET , Yannick LE TIEC , Nicolas POSSEME
IPC分类号： H01L29/772 , H01L21/768
CPC分类号： H01L29/78648 , H01L21/743 , H01L21/76283
摘要： The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.
摘要翻译：场效应晶体管包括依次包括导电支撑衬底，电绝缘层和半导体材料层的衬底。对置电极形成在支撑基板的面向半导体材料层的第一部分中。绝缘图案围绕半导体材料层以描绘第一有源区域并且其部分地穿透到支撑层中以描绘第一部分。导电接触通过绝缘图案从与对电极接触的第一侧表面穿过第二表面。触点电连接到对电极。

3. 发明申请

US20120187488A1 FIELD EFFECT DEVICE PROVIDED WITH A THINNED COUNTER-ELECTRODE AND METHOD FOR FABRICATING 有权
标题翻译：带有削弱计数器电极的场效应装置及其制造方法
公开(公告)号：US20120187488A1
公开(公告)日：2012-07-26
申请号：US13352784
申请日：2012-01-18
申请人： Laurent GRENOUILLET , Maud VINET
发明人： Laurent GRENOUILLET , Maud VINET
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78603 , H01L21/26586 , H01L29/66772 , H01L29/78648
摘要： A field effect device comprises a substrate of semiconductor on insulator type successively provided with a support substrate, an electrically insulating layer and a semiconductor material film. First and second source/drain electrodes are formed in the semiconductor material layer. A conduction channel is formed in the semiconductor material layer and separates the first and second source/drain electrodes. A counter-electrode is formed in the support substrate and faces the first and second source/drain electrodes and the conduction channel. The counter-electrode is formed by a doped area of the support substrate having a first doping impurity concentration which decreases from an interface between the electrically insulating layer and the support substrate.
摘要翻译：场效应器件包括连续设置有支撑衬底的绝缘体半导体衬底，电绝缘层和半导体材料膜。第一和第二源极/漏极形成在半导体材料层中。在半导体材料层中形成导电沟道，并分离第一和第二源极/漏极。在支撑基板上形成对置电极并面对第一和第二源/漏电极和导电沟道。对电极由支撑衬底的掺杂区域形成，其具有从电绝缘层和支撑衬底之间的界面减小的第一掺杂杂质浓度。

4. 发明申请

US20120187489A1 FIELD EFFECT DEVICE PROVIDED WITH A LOCALIZED DOPANT DIFFUSION BARRIER AREA AND FABRICATION METHOD 有权
标题翻译：具有本地化多普勒扩散障碍区域和制造方法的场效应器件
公开(公告)号：US20120187489A1
公开(公告)日：2012-07-26
申请号：US13356975
申请日：2012-01-24
申请人： Laurent GRENOUILLET , Yannick LE TIEC , Nicolas POSSEME , Maud VINET
发明人： Laurent GRENOUILLET , Yannick LE TIEC , Nicolas POSSEME , Maud VINET
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78618 , H01L21/26586 , H01L29/66772 , H01L29/78696
摘要： The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.
摘要翻译：场效应器件包括牺牲栅极电极，其侧壁由形成在半导体材料膜上的横向间隔件覆盖。源极/漏极形成在半导体材料膜中并且布置在栅电极的每一侧上。扩散阻挡元件通过由牺牲栅极留下的空隙注入，以便在侧向间隔物下方形成修改的扩散区域。改性扩散区域是与源/漏电极相比掺杂杂质的迁移率降低的区域。

5. 发明申请

US20090286363A1 METHOD FOR MAKING A TRANSISTOR WITH METALLIC SOURCE AND DRAIN 有权
标题翻译：用金属源和漏极制造晶体管的方法
公开(公告)号：US20090286363A1
公开(公告)日：2009-11-19
申请号：US12433209
申请日：2009-04-30
申请人： Maud VINET , Thierry Poiroux , Bernard Previtali
发明人： Maud VINET , Thierry Poiroux , Bernard Previtali
IPC分类号： H01L21/336 , H01L27/12
CPC分类号： H01L29/41783 , H01L21/823814 , H01L29/41766 , H01L29/517 , H01L29/66628 , H01L29/66636 , H01L29/66643 , H01L29/66772 , H01L29/7834 , H01L29/7839 , H01L29/78648
摘要： Method for making a field effect transistor comprising the following steps: a) make a structure on a substrate, comprising a channel, a gate and a hard mask, b) formation of a dielectric completely covering said structure and locations of a source and a drain of the transistor and a peripheral zone, c) in the dielectric portion, make two holes exposing the sidewalls of the channel, d) deposit a first metallic layer on the walls of the holes, e) silicide said sidewalls, f) deposit a second metallic layer on the first metallic layer, forming the source and the drain of the transistor with the previously silicided portions, g) chemical mechanical polishing of the second metallic layer with a stop on the hard mask.
摘要翻译：制造场效应晶体管的方法，包括以下步骤：a）在包括沟道，栅极和硬掩模的衬底上形成结构，b）形成完全覆盖所述结构的电介质和源极和漏极的位置和c）在电介质部分中，形成露出沟道侧壁的两个孔，d）在孔的壁上沉积第一金属层，e）硅化所述侧壁，f）沉积第二个在第一金属层上形成金属层，用先前的硅化部分形成晶体管的源极和漏极，g）在硬掩模上用停止物对第二金属层进行化学机械抛光。

6. 发明申请

US20150340275A1 METHOD OF PRODUCING A MICROELECTRONIC DEVICE IN A MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATE WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER AN ACTIVE REGION 有权
标题翻译：在单晶半导体衬底中生产微电子器件的方法，其具有在活性区域下部分形成的隔离斜面
公开(公告)号：US20150340275A1
公开(公告)日：2015-11-26
申请号：US14425977
申请日：2012-09-05
申请人： Maud VINET , Nicolas LOUBET , Romain WACQUEZ
发明人： Maud VINET , Nicolas LOUBET , Romain WACQUEZ
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/04 , H01L29/06 , H01L21/3065 , H01L21/311
CPC分类号： H01L21/76224 , H01L21/3065 , H01L21/31116 , H01L21/76232 , H01L21/76283 , H01L21/823481 , H01L29/04 , H01L29/045 , H01L29/0653 , H01L29/66772
摘要： A method of producing a microelectronic device in a substrate including a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, the method including: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device; chemical vapor etching the second semiconductor layer, at a level of a bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region; filling the trench and the etched part of the second semiconductor layer with a dielectric material.
摘要翻译：一种在包括第一半导体层，电介质层和第二单晶半导体层的衬底中制造微电子器件的方法，所述方法包括：通过所述第一半导体层和所述介电层蚀刻沟槽，并且使得所述沟槽限定一个微电子器件的有源区; 根据所述第二半导体层的至少两个晶面，使所述第二半导体层的蚀刻部分在所述有源区的一部分下方延伸，在所述沟槽的底壁的水平面刻蚀所述第二半导体层; 用介电材料填充沟槽和第二半导体层的蚀刻部分。

7. 发明申请

US20080297180A1 DEVICE FOR MEASURING METAL/SEMICONDUCTOR CONTACT RESISTIVITY 有权
标题翻译：用于测量金属/半导体接触电阻的装置
公开(公告)号：US20080297180A1
公开(公告)日：2008-12-04
申请号：US12123758
申请日：2008-05-20
申请人： Maud VINET
发明人： Maud VINET
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： H01L22/34 , H01L2924/0002 , Y10T29/49004 , H01L2924/00
摘要： A device for measuring the resistivity ρc of an interface between a semiconductor and a metal, comprising at least: one dielectric layer, at least one semiconductor-based element of a substantially rectangular shape, which is arranged on the dielectric layer, having a lengthwise L and widthwise W face in contact with the dielectric layer and having a thickness t, at least two interface portions containing the metal or an alloy of said semiconductor and said metal, each of the two opposing faces of the semiconductor element, having a surface equal to t×W and being perpendicular to the face in contact with the dielectric layer, being completely covered by one of the interface portions.
摘要翻译：一种用于测量半导体和金属之间的界面的电阻率rhoc的装置，包括至少一个电介质层，至少一个基本矩形形状的基于半导体的元件，其布置在电介质层上，具有纵向L 宽度方向W表面与电介质层接触且具有厚度t，至少两个界面部分包含所述半导体和所述金属的金属或合金，半导体元件的两个相对面中的每一个具有等于 txW并且垂直于与介电层接触的面，被完全被接口部分中的一个覆盖。

8. 发明申请

US20080200001A1 METHOD OF PRODUCING A TRANSISTOR 有权
标题翻译：制造晶体管的方法
公开(公告)号：US20080200001A1
公开(公告)日：2008-08-21
申请号：US12030672
申请日：2008-02-13
申请人： Laurent CLAVELIER , Frederic MAYER , Maud VINET , Simon DELEONIBUS
发明人： Laurent CLAVELIER , Frederic MAYER , Maud VINET , Simon DELEONIBUS
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L29/66325 , H01L29/66659 , H01L29/7391 , H01L29/78
摘要： Method of producing a transistor, comprising in particular the steps of:producing a first etching mask on a gate layer, one edge of the first mask forming a pattern of the first edge of a gate of the transistor,etching the gate layer according to the first etching mask,first ion implantation in a part of the substrate not covered by the gate layer,trimming the first etching mask over a length equal to a gate length of the transistor,producing a second etching mask on the gate layer,removing the first etching masketching the gate layer according to the second etching mask,second ion implantation in another part of the substrate.
摘要翻译：制造晶体管的方法，其特别包括以下步骤：在栅极层上制造第一蚀刻掩模，第一掩模的一个边缘形成晶体管的栅极的第一边缘的图案，根据该栅极层蚀刻栅极层第一蚀刻掩模，在未被栅极层覆盖的衬底的一部分中的第一离子注入，在等于晶体管的栅极长度的长度上修整第一蚀刻掩模，在栅极层上产生第二蚀刻掩模，去除第一蚀刻掩模蚀刻掩模根据第二蚀刻掩模蚀刻栅极层，在衬底的另一部分中进行第二离子注入。

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