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1. 发明授权

US08853785B2 Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit 有权
标题翻译：具有静电耦合MOS晶体管的集成电路及其制造方法
公开(公告)号：US08853785B2
公开(公告)日：2014-10-07
申请号：US12868488
申请日：2010-08-25
申请人： Emmanuel Augendre , Maud Vinet , Laurent Clavelier , Perrine Batude
发明人： Emmanuel Augendre , Maud Vinet , Laurent Clavelier , Perrine Batude
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L21/8221 , H01L27/0688 , H01L27/11
摘要： An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.
摘要翻译：一种集成电路，至少包括：第一MOS晶体管; 配置在所述第一MOS晶体管上的第二MOS晶体管，所述第二MOS晶体管在至少一个包含两个近似平行的主面的半导体层中包括沟道区; 至少一个导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 至少布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且在与半导体层的两个主面平行的平面中的第二晶体管的沟道区域的一部分被包括在投影在所述平面中的导电材料部分的一部分中。

2. 发明授权

US08809964B2 Method of adjusting the threshold voltage of a transistor by a buried trapping layer 有权
标题翻译：通过埋置捕获层调节晶体管的阈值电压的方法
公开(公告)号：US08809964B2
公开(公告)日：2014-08-19
申请号：US12865549
申请日：2009-02-11
申请人： François Andrieu , Emmanuel Augendre , Laurent Clavelier , Marek Kostrzewa
发明人： François Andrieu , Emmanuel Augendre , Laurent Clavelier , Marek Kostrzewa
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/42348 , H01L21/84 , H01L27/1203 , H01L29/792
摘要： An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.
摘要翻译：一种用于生产电子组件的电子组件和相关方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，并且其中在预定的第一深度形成第一捕集区。第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。来自第一晶体管的有用信息包括该晶体管内的电荷传输。可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。

3. 发明授权

US07989327B2 Manufacturing method for a semi-conductor on insulator substrate comprising a localised Ge enriched step 有权
标题翻译：一种半导体绝缘体衬底的制造方法，包括局部富锗步骤
公开(公告)号：US07989327B2
公开(公告)日：2011-08-02
申请号：US12340839
申请日：2008-12-22
申请人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
发明人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
IPC分类号： H01L21/20
CPC分类号： H01L21/32105 , H01L21/7624
摘要： A method of manufacturing a semi-conductor on insulator substrate from an SOI substrate, wherein a Si1-xGex layer is formed on a superficial layer of silicon having a buried electrical insulating layer. A silicon oxide layer is formed on the Si1-xGex layer. The resulting stack of silicon, Si1-xGex and silicon oxide layers is etched up to the buried insulating layer leaving an island of the stack, or up to the superficial layer leaving a zone of silicon and an island of the stack. A mask is formed to protect against oxidation on the etched structure, wherein the protective mask only leaves visible the silicon oxide layer of the island. The germanium of the Si1-xGex layer is condensed on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the insulating layer, with a silicon oxide layer on top of it.
摘要翻译：一种从SOI衬底制造绝缘体上半导体衬底的方法，其中在具有掩埋电绝缘层的硅的表面层上形成Si1-xGex层。在Si1-xGex层上形成氧化硅层。所得到的硅叠层Si1-xGex和氧化硅层被蚀刻到掩埋绝缘层上，留下堆叠的岛，或直到离开硅区域和堆叠岛的表层。形成掩模以防止在蚀刻结构上的氧化，其中保护掩模仅使岛的氧化硅层可见。 Si1-xGex层的锗在岛上被冷凝，以获得在绝缘层上富含锗或甚至一层锗的层，其上面具有氧化硅层。

4. 发明申请

US20100221891A1 METHOD OF PRODUCING A HYBRID SUBSTRATE BY PARTIAL RECRYSTALLIZATION OF A MIXED LAYER 有权
标题翻译：通过混合层的部分再结晶生产混合基材的方法
公开(公告)号：US20100221891A1
公开(公告)日：2010-09-02
申请号：US12705039
申请日：2010-02-12
申请人： FRANCK FOURNEL , Thomas Signamarcheix , Laurent Clavelier , Chrystel Deguet
发明人： FRANCK FOURNEL , Thomas Signamarcheix , Laurent Clavelier , Chrystel Deguet
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： A method of producing a hybrid substrate includes preparing a monocrystalline first substrate to obtain two surface portions. A temporary substrate is prepared including a mixed layer along which extends one surface portion and is formed of first areas and adjacent different second areas of amorphous material, the second areas forming at least part of the free surface of the first substrate. The first substrate is bonded to the other surface portion with the same crystal orientation as the first surface portion, by molecular bonding over at least the amorphous areas. A solid phase recrystallization of at least part of the amorphous areas according to the crystal orientation of the first substrate is selectively carried and the two surface portions are separated.
摘要翻译：制造混合基板的方法包括制备单晶第一基板以获得两个表面部分。制备临时衬底，其包括混合层，沿其延伸一个表面部分并且由第一区域和相邻的不同第二区域的非晶材料形成，第二区域形成第一衬底的至少部分自由表面。第一衬底通过在至少非晶区上分子键合而与第一表面部分具有相同的晶体取向而与另一表面部分结合。选择性地承载根据第一基板的晶体取向的至少一部分非晶区域的固相重结晶，并分离两个表面部分。

5. 发明申请

US20090325335A1 HETEROGENEOUS SUBSTRATE INCLUDING A SACRIFICIAL LAYER, AND A METHOD OF FABRICATING IT 有权
标题翻译：异质基底包括一个非常复杂的层，以及一种制造它的方法
公开(公告)号：US20090325335A1
公开(公告)日：2009-12-31
申请号：US12488854
申请日：2009-06-22
申请人： François Perruchot , Bernard Diem , Vincent Larrey , Laurent Clavelier , Emmanuel Defay
发明人： François Perruchot , Bernard Diem , Vincent Larrey , Laurent Clavelier , Emmanuel Defay
IPC分类号： H01L21/302 , H01L21/02
CPC分类号： B81C1/00595 , B81B2201/0271 , B81C2201/0109 , B81C2201/014
摘要： The invention relates to a method of making a component from a heterogeneous substrate comprising first and second portions in at least one monocrystalline material, and a sacrificial layer constituted by at least one stack of at least one layer of monocrystalline Si situated between two layers of monocrystalline SiGe, the stack being disposed between said first and second portions of monocrystalline material, wherein the method consists in etching said stack by making: e) at least one opening in the first and/or second portion and the first and/or second layer of SiGe so as to reach the layer of Si; and f) eliminating all or part of the layer of Si.
摘要翻译：本发明涉及一种从包含至少一种单晶材料中的第一和第二部分的异质衬底制备组分的方法，以及由位于两层单晶之间的至少一层单晶硅的至少一个叠层构成的牺牲层 SiGe，堆叠设置在单晶材料的第一和第二部分之间，其中该方法包括通过以下步骤蚀刻所述堆叠：e）在第一和/或第二部分中的至少一个开口，以及第一和/ SiGe，以达到Si层; 和f）消除Si的全部或部分层。

6. 发明授权

US07625811B2 Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures 有权
标题翻译：用于制造不同的第一和第二有源半导体区的方法及其用于制造C-MOS结构的方法
公开(公告)号：US07625811B2
公开(公告)日：2009-12-01
申请号：US11584635
申请日：2006-10-23
申请人： Jean-Charles Barbe , Laurent Clavelier , Benoit Vianay , Yves Morand
发明人： Jean-Charles Barbe , Laurent Clavelier , Benoit Vianay , Yves Morand
IPC分类号： H01L21/20 , H01L21/36 , H01L21/8238
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L21/823807 , H01L21/84 , H01L27/1203
摘要： A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces of the first and second active zones also present the advantage of being in the same plane. Such a method consists in particular in producing the second active zones by a crystallization step of the second semi-conducting material in monocrystalline form, from patterns made of second semi-conducting material in polycrystalline and/or amorphous form and from interface regions between said patterns and preselected first active zones. Moreover, the support is formed by stacking of a substrate and of an electrically insulating thin layer, the front face of the electrically insulating thin layer forming the front face of the support.
摘要翻译：根据本发明的方法使得能够在支撑体的前表面上产生第一和第二活性区域，所述区域分别由彼此不同的优选具有相同晶体结构的第一和第二单晶半导体材料形成。第一和第二活动区域的前表面也具有处于同一平面上的优点。这种方法特别在于通过第二半导体材料以单晶形式的结晶步骤从多晶和/或无定形形式的第二半导体材料制成的图案和由所述图案之间的界面区域产生第二活性区域和预选的第一活动区域。此外，通过堆叠基板和电绝缘薄层形成支撑体，电绝缘薄层的前表面形成支撑体的前表面。

7. 发明申请

US20080153267A1 METHOD FOR MANUFACTURING A SOI SUBSTRATE ASSOCIATING SILICON BASED AREAS AND GAAS BASED AREAS 失效
标题翻译：制造相关硅基区域和基于GAAS的区域的SOI衬底的方法
公开(公告)号：US20080153267A1
公开(公告)日：2008-06-26
申请号：US11959924
申请日：2007-12-19
申请人： Laurent CLAVELIER , Chrystel DEGUET
发明人： Laurent CLAVELIER , Chrystel DEGUET
IPC分类号： H01L21/205
CPC分类号： H01L31/184 , C30B19/12 , C30B23/025 , C30B25/18 , C30B29/08 , C30B29/42 , G02B6/12004 , G02B6/43 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02543 , H01L21/02546 , H01L21/02625 , H01L21/02639 , H01L21/02647 , H01L21/8258 , H01L21/84 , H01L27/1203 , Y02E10/544
摘要： The invention relates to a method for manufacturing an SOI substrate, associating silicon based areas and areas of GaAs based material at the thin layer of the SOI substrate, the SOI substrate comprising a silicon support supporting successively a layer of dielectric material and a thin layer of silicon. The method comprises the following steps: supply of a SOI substrate comprising a silicon support mismatched by an angle of between 2° and 10° inclusive, the thin silicon based layer being oriented parallel to the plane (001) or (010), or (100) or (110) or (101) or (011) or (111), preservation of at least one area of the thin silicon layer, elimination of at least one non-preserved area of the thin silicon layer until the layer of dielectric material is revealed, opening, in said non-preserved area, of the layer of dielectric material until the silicon support is revealed, growth, from the silicon of the support revealed by said opening and by liquid phase epitaxy or by lateral epitaxy, of mismatched germanium on the layer of dielectric material revealed, growth of GaAs based material from the mismatched germanium obtained in the preceding step.
摘要翻译：本发明涉及一种用于制造SOI衬底的方法，该SOI衬底的薄层将基于硅的区域和GaAs基材料的区域相关联，所述SOI衬底包括依次支撑介电材料层和硅层的薄层硅。该方法包括以下步骤：提供包含不同于2°和10°之间角度的硅载体的SOI衬底，所述薄硅基层平行于平面（001）或（010）或（010）定向，或（ 100）或（110）或（101）或（011）或（111），保存薄硅层的至少一个区域，消除薄硅层的至少一个未保存区域直到电介质层在所述非保存区域中，揭示介质材料层的开口，直到硅支撑体露出，从由所述开口显示的支撑体的硅和通过液相外延或横向外延生长的不匹配的介电材料层上的锗显示出，在前面步骤中获得的来自错配锗的GaAs基材料的生长。

8. 发明申请

US20130146955A1 ELECTRONIC CHIP HAVING CHANNELS THROUGH WHICH A HEAT TRANSPORT COOLANT CAN FLOW, ELECTRONIC COMPONENTS AND COMMUNICATION ARM INCORPORATING SAID CHIP 有权
标题翻译：通过热交换冷却液流通的通道的电子芯片，电子组件和通信芯片
公开(公告)号：US20130146955A1
公开(公告)日：2013-06-13
申请号：US13700918
申请日：2011-05-31
申请人： Yvan Avenas , Jean-Christophe Crebier , Julie Widiez , Laurent Clavelier , Kremena Vladimirova
发明人： Yvan Avenas , Jean-Christophe Crebier , Julie Widiez , Laurent Clavelier , Kremena Vladimirova
IPC分类号： H01L23/46
CPC分类号： H01L23/46 , H01L23/473 , H01L25/074 , H01L33/648 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to an electronic chip, comprising: a semiconductor substrate (6) having an active area (8) formed by at least one P doped region and at least one N doped region which form one or more P-N junctions through which most of the useful current flows when said electronic chip is in a conductive state, and at least one channel (44) through which a heat transport coolant can flow, the channel(s) passing through at least said P or N doped region of the active area. Each channel (44) is rectilinear and passes through the substrate (6) in a direction which is collinear with a direction F to the nearest ±45°, where the direction F is perpendicular to the plane of the substrate.
摘要翻译：本发明涉及一种电子芯片，包括：半导体衬底（6），具有由至少一个P掺杂区形成的有源区（8）和形成一个或多个PN结的至少一个N掺杂区，当所述电子芯片处于导电状态时有用的电流流动，以及至少一个通道（44），热传输冷却剂可以通过该通道流过，所述通道至少穿过有源区域的所述P或N掺杂区域。每个通道（44）是直线的，并且沿与方向F共线的方向通过基板（6）至最接近的±45°，其中方向F垂直于基板的平面。

9. 发明授权

US08445122B2 Data storage medium and associated method 有权
标题翻译：数据存储介质及相关方法
公开(公告)号：US08445122B2
公开(公告)日：2013-05-21
申请号：US12338281
申请日：2008-12-18
申请人： Chrystel Deguet , Laurent Clavelier , Franck Fournel , Jean-Sebastien Moulet
发明人： Chrystel Deguet , Laurent Clavelier , Franck Fournel , Jean-Sebastien Moulet
IPC分类号： G11C11/22 , H01L21/02
CPC分类号： G11B9/02 , B82Y10/00 , G11B5/743 , G11B9/1472 , G11B9/149 , Y10T428/115
摘要： A data storage medium includes a carrier substrate having an electrode layer on the surface thereof and a sensitive material layer extending along the electrode layeradapted to be locally modified between two electrical states by the action of a localized electric field. A reference plane extends globally parallel to the sensitive material layer and is configured to accommodate at least one element for application of an electrostatic field in combination with the electrode layer the electrode layer including a plurality of conductive portions having a dimension at most equal to 100 nm in at least one direction parallel to the reference plane and separated by at least one electrically insulative zone, where at least some of the conductive portions are electrically interconnected, the conductive portions defining data write/read locations within the sensitive material layer.
摘要翻译：数据存储介质包括其表面上具有电极层的载体衬底和沿着电极层延伸的敏感材料层，所述敏感材料层通过局部电场的作用被局部地改变为两个电气状态。参考平面全局平行于敏感材料层延伸，并且被配置为容纳用于与电极层组合施加静电场的至少一个元件，该电极层包括具有至多等于100nm的尺寸的多个导电部分在平行于参考平面的至少一个方向上并且由至少一个电绝缘区隔开，其中至少一些导电部分电互连，导电部分在敏感材料层内限定数据写/读位置。

10. 发明授权

US08318555B2 Method of producing a hybrid substrate having a continuous buried electrically insulating layer 有权
标题翻译：一种具有连续掩埋电绝缘层的混合基板的制造方法
公开(公告)号：US08318555B2
公开(公告)日：2012-11-27
申请号：US13125953
申请日：2009-10-29
申请人： Thomas Signamarcheix , Franck Fournel , Laurent Clavelier , Chrystel Deguet
发明人： Thomas Signamarcheix , Franck Fournel , Laurent Clavelier , Chrystel Deguet
IPC分类号： H01L21/84
CPC分类号： H01L21/76254
摘要： A method for producing a hybrid substrate includes preparing a first substrate including a mixed layer and an underlying electrically insulating continuous layer, the mixed layer made up of first single-crystal areas and second adjacent amorphous areas, the second areas making up at least part of the free surface of the first substrate. A second substrate is bonded to the first substrate, the second substrate including on the surface thereof, a reference layer with a predetermined crystallographic orientation. The first substrate is bonded to the second substrate by hydrophobic molecular bonding of at least the amorphous areas. A recrystallization of at least part of the amorphous areas to solid phase is carried out according to the crystallographic orientation of the reference layer, and the two substrates are separated at the bonding interface.
摘要翻译：一种混合基板的制造方法，其特征在于，制备包括混合层和下层电绝缘连续层的第一基板，由第一单晶区域和第二相邻非晶区域构成的混合层，构成第第一基板的自由表面。第二衬底被结合到第一衬底，第二衬底在其表面上包括具有预定晶体取向的参考层。第一衬底通过至少非晶区域的疏水分子键合而结合到第二衬底。根据参考层的结晶取向进行至少部分非晶区域至固相的再结晶，两个基板在键合界面处分离。

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