专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130262837A1 PROGRAMMABLE COUNTERS FOR COUNTING FLOATING-POINT OPERATIONS IN SMD PROCESSORS 有权
标题翻译：用于计数SMD处理器浮点操作的可编程计数器
公开(公告)号：US20130262837A1
公开(公告)日：2013-10-03
申请号：US13434564
申请日：2012-03-29
申请人： Laura A. Knauth , Matthew C. Merten , Ronak Singhal , Hugh M. Caffey
发明人： Laura A. Knauth , Matthew C. Merten , Ronak Singhal , Hugh M. Caffey
IPC分类号： G06F9/302
CPC分类号： G06F9/3013 , G06F9/30109 , G06F9/30112 , G06F11/3409 , G06F11/3466 , G06F2201/88
摘要： A processor includes an execution unit to execute instructions, where each operand of each executed instruction has one or more elements of an element size and at least one operand of the instruction corresponds to a register of a register size. The processor further includes a counter configured to count a number of instructions that have been executed by the execution unit associated with a particular combination of register size and element size.
摘要翻译：处理器包括执行指令的执行单元，其中每个执行指令的每个操作数具有元素大小的一个或多个元素，并且指令的至少一个操作数对应于寄存器大小的寄存器。处理器还包括计数器，其被配置为对由执行单元执行的与寄存器大小和元素大小的特定组合相关联的指令数进行计数。

2. 发明授权

US09092214B2 SIMD processor with programmable counters externally configured to count executed instructions having operands of particular register size and element size combination 有权
标题翻译：具有可编程计数器的SIMD处理器，其外部配置为对具有特定寄存器大小和元件大小组合的操作数的执行指令进行计数
公开(公告)号：US09092214B2
公开(公告)日：2015-07-28
申请号：US13434564
申请日：2012-03-29
申请人： Laura A. Knauth , Matthew C. Merten , Ronak Singhal , Hugh M. Caffey
发明人： Laura A. Knauth , Matthew C. Merten , Ronak Singhal , Hugh M. Caffey
IPC分类号： G06F15/80 , G06F9/30 , G06F11/34
CPC分类号： G06F9/3013 , G06F9/30109 , G06F9/30112 , G06F11/3409 , G06F11/3466 , G06F2201/88
摘要： A processor includes an execution unit to execute instructions, where each operand of each executed instruction has one or more elements of an element size and at least one operand of the instruction corresponds to a register of a register size. The processor further includes a counter configured to count a number of instructions that have been executed by the execution unit associated with a particular combination of register size and element size.
摘要翻译：处理器包括执行指令的执行单元，其中每个执行指令的每个操作数具有元素大小的一个或多个元素，并且指令的至少一个操作数对应于寄存器大小的寄存器。处理器还包括计数器，其被配置为对由执行单元执行的与寄存器大小和元素大小的特定组合相关联的指令数进行计数。

3. 发明授权

US09582275B2 Method and apparatus for obtaining a call stack to an event of interest and analyzing the same 有权
标题翻译：用于获得对感兴趣的事件的调用栈的分析的方法和装置
公开(公告)号：US09582275B2
公开(公告)日：2017-02-28
申请号：US13118766
申请日：2011-05-31
申请人： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
发明人： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F11/34
CPC分类号： G06F9/30058 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/3016 , G06F11/3409 , G06F11/3476 , G06F11/348 , G06F12/0875
摘要： In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括性能监视器，其包括最后一个分支记录（LBR）堆栈，以将呼叫堆栈存储到感兴趣的事件，响应于该事件的触发来收集呼叫栈。处理器还包括控制LBR堆栈以调用堆栈模式操作的逻辑，使得从叶片功能返回时清除叶子功能的调用指令的条目。描述和要求保护其他实施例。

4. 发明申请

US20120311307A1 Method And Apparatus For Obtaining A Call Stack To An Event Of Interest And Analyzing The Same 有权
标题翻译：方法和设备获取一个调用堆栈到一个有趣的事件和分析它
公开(公告)号：US20120311307A1
公开(公告)日：2012-12-06
申请号：US13118766
申请日：2011-05-31
申请人： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
发明人： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/3016 , G06F11/3409 , G06F11/3476 , G06F11/348 , G06F12/0875
摘要： In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括性能监视器，其包括最后一个分支记录（LBR）堆栈，以将呼叫堆栈存储到感兴趣的事件，响应于该事件的触发来收集呼叫栈。处理器还包括控制LBR堆栈以调用堆栈模式操作的逻辑，使得从叶片功能返回时清除叶子功能的调用指令的条目。描述和要求保护其他实施例。

5. 发明申请

US20150378412A1 Method And Apparatus To Prevent Voltage Droop In A Computer 有权
标题翻译：防止电脑电压下降的方法和装置
公开(公告)号：US20150378412A1
公开(公告)日：2015-12-31
申请号：US14318999
申请日：2014-06-30
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson
IPC分类号： G06F1/28 , G06F1/26 , G06F12/08 , G06F1/32
CPC分类号： G06F1/3206 , G06F9/3824 , G06F9/3836
摘要： In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个包括第一核心的核心。第一核心包括执行一个或多个存储器指令的存储器执行逻辑，将存储器指令输出到存储器执行逻辑的存储器调度逻辑以及无效存储器指令跟踪逻辑。反应性存储器指令跟踪逻辑是检测与执行至少一个存储器指令相关联的存储器指令高功率事件的开始，并且向存储器调度逻辑指示将存储器指令的输出调节到存储器执行逻辑响应于检测到存储器指令高功率事件的发生。处理器还包括耦合到至少一个核的高速缓存存储器。描述和要求保护其他实施例。

6. 发明授权

US09134788B2 Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit 有权
标题翻译：能量效率和节能的方法，装置和系统，包括检测和控制处理电路中的电流斜坡
公开(公告)号：US09134788B2
公开(公告)日：2015-09-15
申请号：US13340511
申请日：2011-12-29
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
摘要翻译：一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示作为执行第二组操作的结果的处理器。当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

7. 发明申请

US20140189306A1 ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION 有权
标题翻译：增强环路检测器驱动逻辑优化
公开(公告)号：US20140189306A1
公开(公告)日：2014-07-03
申请号：US13728273
申请日：2012-12-27
申请人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
发明人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/3885
摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.
摘要翻译：在处理器中提供增强的循环流检测机制以降低功耗。处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

8. 发明申请

US20140025901A1 TECHNIQUE FOR USING MEMORY ATTRIBUTES 有权
标题翻译：使用存储器属性的技术
公开(公告)号：US20140025901A1
公开(公告)日：2014-01-23
申请号：US14033463
申请日：2013-09-21
申请人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
发明人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

9. 发明申请

US20130205119A1 INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS 有权
标题翻译：指令和逻辑测试交易执行状态
公开(公告)号：US20130205119A1
公开(公告)日：2013-08-08
申请号：US13538951
申请日：2012-06-29
申请人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
发明人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
IPC分类号： G06F9/46
CPC分类号： G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

10. 发明授权

US07516313B2 Predicting contention in a processor 失效
标题翻译：预测处理器中的争用
公开(公告)号：US07516313B2
公开(公告)日：2009-04-07
申请号：US11027392
申请日：2004-12-29
申请人： Bratin Saha , Matthew C. Merten , Sebastien Hily , David A. Koufaty , Per Hammarlund
发明人： Bratin Saha , Matthew C. Merten , Sebastien Hily , David A. Koufaty , Per Hammarlund
IPC分类号： G06F13/376 , G06F9/38 , G06F13/18
CPC分类号： G06F9/3851 , G06F9/526
摘要： In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于预测在程序中要执行的操作的竞争的预测器。可以基于预测的结果来处理该操作，该结果可以基于多个独立的预测。在一个实施例中，如果没有预测到争用，则可以优化操作。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式