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1. 发明申请

US20150346804A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT 有权
标题翻译：用于能源效率和能源保护的方法，装置和系统，包括检测和控制处理电路中的电流RAM
公开(公告)号：US20150346804A1
公开(公告)日：2015-12-03
申请号：US14823994
申请日：2015-08-11
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
摘要翻译：一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示作为执行第二组操作的结果的处理器。当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

2. 发明申请

US20120221871A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT 有权
标题翻译：用于能源效率和能源保护的方法，装置和系统，包括检测和控制处理电路中的电流RAM
公开(公告)号：US20120221871A1
公开(公告)日：2012-08-30
申请号：US13340511
申请日：2011-12-29
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
摘要翻译：一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示作为执行第二组操作的结果的处理器。当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

3. 发明授权

US09134788B2 Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit 有权
标题翻译：能量效率和节能的方法，装置和系统，包括检测和控制处理电路中的电流斜坡
公开(公告)号：US09134788B2
公开(公告)日：2015-09-15
申请号：US13340511
申请日：2011-12-29
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
摘要翻译：一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示作为执行第二组操作的结果的处理器。当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

4. 发明申请

US20150378412A1 Method And Apparatus To Prevent Voltage Droop In A Computer 有权
标题翻译：防止电脑电压下降的方法和装置
公开(公告)号：US20150378412A1
公开(公告)日：2015-12-31
申请号：US14318999
申请日：2014-06-30
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson
IPC分类号： G06F1/28 , G06F1/26 , G06F12/08 , G06F1/32
CPC分类号： G06F1/3206 , G06F9/3824 , G06F9/3836
摘要： In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个包括第一核心的核心。第一核心包括执行一个或多个存储器指令的存储器执行逻辑，将存储器指令输出到存储器执行逻辑的存储器调度逻辑以及无效存储器指令跟踪逻辑。反应性存储器指令跟踪逻辑是检测与执行至少一个存储器指令相关联的存储器指令高功率事件的开始，并且向存储器调度逻辑指示将存储器指令的输出调节到存储器执行逻辑响应于检测到存储器指令高功率事件的发生。处理器还包括耦合到至少一个核的高速缓存存储器。描述和要求保护其他实施例。

5. 发明申请

US20140189306A1 ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION 有权
标题翻译：增强环路检测器驱动逻辑优化
公开(公告)号：US20140189306A1
公开(公告)日：2014-07-03
申请号：US13728273
申请日：2012-12-27
申请人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
发明人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/3885
摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.
摘要翻译：在处理器中提供增强的循环流检测机制以降低功耗。处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

6. 发明申请

US20140025901A1 TECHNIQUE FOR USING MEMORY ATTRIBUTES 有权
标题翻译：使用存储器属性的技术
公开(公告)号：US20140025901A1
公开(公告)日：2014-01-23
申请号：US14033463
申请日：2013-09-21
申请人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
发明人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

7. 发明申请

US20130205119A1 INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS 有权
标题翻译：指令和逻辑测试交易执行状态
公开(公告)号：US20130205119A1
公开(公告)日：2013-08-08
申请号：US13538951
申请日：2012-06-29
申请人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
发明人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
IPC分类号： G06F9/46
CPC分类号： G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

8. 发明授权

US07516313B2 Predicting contention in a processor 失效
标题翻译：预测处理器中的争用
公开(公告)号：US07516313B2
公开(公告)日：2009-04-07
申请号：US11027392
申请日：2004-12-29
申请人： Bratin Saha , Matthew C. Merten , Sebastien Hily , David A. Koufaty , Per Hammarlund
发明人： Bratin Saha , Matthew C. Merten , Sebastien Hily , David A. Koufaty , Per Hammarlund
IPC分类号： G06F13/376 , G06F9/38 , G06F13/18
CPC分类号： G06F9/3851 , G06F9/526
摘要： In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于预测在程序中要执行的操作的竞争的预测器。可以基于预测的结果来处理该操作，该结果可以基于多个独立的预测。在一个实施例中，如果没有预测到争用，则可以优化操作。描述和要求保护其他实施例。

9. 发明授权

US09442729B2 Minimizing bandwidth to track return targets by an instruction tracing system 有权
标题翻译：最小化带宽以通过指令跟踪系统跟踪返回目标
公开(公告)号：US09442729B2
公开(公告)日：2016-09-13
申请号：US13890654
申请日：2013-05-09
申请人： Beeman C. Strong , Matthew C. Merten , Tong Li
发明人： Beeman C. Strong , Matthew C. Merten , Tong Li
IPC分类号： G06F9/30 , H04L29/06 , G06F9/38 , G06F11/36 , G06F11/34
CPC分类号： G06F9/30145 , G06F9/3806 , G06F9/3857 , G06F11/3476 , G06F11/3636
摘要： A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the disclosure an instruction fetch unit comprising a return stack buffer (RSB) to predict a target address of a return (RET) instruction corresponding to a call (CALL) instruction. The processing device further includes a retirement unit comprising an instruction tracing module to initiate instruction tracing for instructions executed by the processing device, determine whether the target address of the RET instruction was mispredicted, determine a value of call depth counter (CDC) maintained by the instruction tracing module, and when the target address of the RET instruction was not mispredicted and when the value of the CDC is greater than zero, generate an indication that the RET instruction branches to a next linear instruction after the corresponding CALL instruction.
摘要翻译：公开了一种通过指令跟踪系统实现最小化带宽以跟踪返回目标的处理设备。本公开的处理装置包括一个指令提取单元，该单元包括用于预测与一个调用（CALL）指令相对应的返回（RET）指令的目标地址的返回栈缓冲器（RSB）。所述处理装置还包括退出单元，所述退出单元包括指令跟踪模块，用于启动由所述处理设备执行的指令的指令跟踪，确定所述RET指令的目标地址是否被错误预测，确定由所述处理设备维护的所述呼叫深度计数器指令跟踪模块，并且当RET指令的目标地址未被错误预测时，并且当CDC的值大于零时，生成指令在相应的CALL指令之后分支到下一个线性指令。

10. 发明授权

US09292288B2 Systems and methods for flag tracking in move elimination operations 有权
标题翻译：移动消除操作中标志跟踪的系统和方法
公开(公告)号：US09292288B2
公开(公告)日：2016-03-22
申请号：US13861009
申请日：2013-04-11
申请人： Vijaykumar B. Kadgi , Jeremy R. Anderson , James D. Hadley , Tong Li , Matthew C. Merten
发明人： Vijaykumar B. Kadgi , Jeremy R. Anderson , James D. Hadley , Tong Li , Matthew C. Merten
IPC分类号： G06F9/30 , G06F9/45 , G06F9/38
CPC分类号： G06F9/30105 , G06F8/443 , G06F9/30032 , G06F9/30094 , G06F9/30098 , G06F9/3013 , G06F9/30181 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.
摘要翻译：涉及移动消除的数据处理操作中标志跟踪的系统和方法。示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

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