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1. 发明授权

US5795685A Simple repair method for phase shifting masks 失效
标题翻译：相位掩模的简单修复方法
公开(公告)号：US5795685A
公开(公告)日：1998-08-18
申请号：US783631
申请日：1997-01-14
申请人： Lars W. Liebmann , Burn Jeng Lin , Mark O. Neisser
发明人： Lars W. Liebmann , Burn Jeng Lin , Mark O. Neisser
IPC分类号： G03F1/26 , G03F1/72 , H01L21/027 , G03F9/00
CPC分类号： G03F1/26 , G03F1/72
摘要： A method and apparatus for correcting defects in a phase shift mask to be used in photolithography. More specifically, the method of the invention includes creating a second repair mask which contains phase shifters. Regions surrounding the defects on the first mask are made opaque. The design circuitry located in these defective regions is copied onto the second mask. During a second exposure the design circuitry is placed onto the semiconductor wafer. Therefore, this method and apparatus provides an inexpensive solution to a difficult problem.
摘要翻译：一种用于校正用于光刻中的相移掩模中的缺陷的方法和装置。更具体地，本发明的方法包括创建包含移相器的第二修复掩模。围绕第一掩模上的缺陷的区域变得不透明。位于这些缺陷区域中的设计电路被复制到第二掩模上。在第二曝光期间，将设计电路放置在半导体晶片上。因此，该方法和装置为困难的问题提供了便宜的解决方案。

2. 发明授权

US08516403B2 Multiple patterning layout decomposition for ease of conflict removal 有权
标题翻译：多重图案化布局分解，便于冲突删除
公开(公告)号：US08516403B2
公开(公告)日：2013-08-20
申请号：US13223844
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction. The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features. The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.
摘要翻译：提供了一种用于具有冲突消除意识着色的多重图案化光刻的机构。该机制使得多个图案化着色意识到冲突移除开销。着色解决方案明确地将冲突移除的容易性作为着色目标之一。该机制预先计算出每个方向上可以移动多少形状。该机制生成一个冲突图，其中节点表示布局中的形状，边缘表示形状之间的冲突。该机制基于冲突特征之间的可用空间松弛来为边缘分配权重。该机构然后使用重量来引导多个图案化着色。该机制优先处理具有较高权重的冲突特征，以分配不同的颜色。

3. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

4. 发明授权

US08225255B2 Placement and optimization of process dummy cells 有权
标题翻译：过程虚拟细胞的放置和优化
公开(公告)号：US08225255B2
公开(公告)日：2012-07-17
申请号：US12124472
申请日：2008-05-21
申请人： Xu Ouyang , Geng Han , Lars W. Liebmann
发明人： Xu Ouyang , Geng Han , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G11C29/24 , G06F2217/12 , G11C5/02 , H01L27/0203 , H01L27/105 , Y02P90/265
摘要： A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.
摘要翻译：与存储器阵列的内部存储单元相关地布置处理虚设单元的方法包括：（a）计算存储器阵列的初始处理性能参数; （b）改变电连接到内部单元的层的虚拟单元布局配置; （c）为内部存储单元和改变的布局配置处理虚拟单元应用光刻模拟和屈服模型; 和（d）重复步骤（b）和（c），直到产率最大化。可以进行检查，以确保有足够的空间进行更改，并且对相邻电路没有明显的不利影响。过程性能参数可以是产量或内部存储器单元的处理窗口。

5. 发明授权

US08103983B2 Electrically-driven optical proximity correction to compensate for non-optical effects 有权
标题翻译：电动光学接近校正补偿非光学效果
公开(公告)号：US08103983B2
公开(公告)日：2012-01-24
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

6. 发明申请

US20100122231A1 ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS 有权
标题翻译：电动驱动光学近似校正补偿非光学效应
公开(公告)号：US20100122231A1
公开(公告)日：2010-05-13
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

7. 发明授权

US07607114B2 Designer's intent tolerance bands for proximity correction and checking 失效
标题翻译：设计师的意图容差带用于近距离校正和检查
公开(公告)号：US07607114B2
公开(公告)日：2009-10-20
申请号：US11778302
申请日：2007-07-16
申请人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
发明人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译：通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束特征对其他层的影响。该方法可以在用于在计算机系统上执行的计算机程序产品中实现。所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

8. 发明授权

US06964032B2 Pitch-based subresolution assist feature design 失效
标题翻译：基于间距的分解辅助功能设计
公开(公告)号：US06964032B2
公开(公告)日：2005-11-08
申请号：US10378579
申请日：2003-02-28
申请人： Lars W. Liebmann , Allen H. Gabor , Ronald L. Gordon , Carlos A. Fonseca , Martin Burkhardt
发明人： Lars W. Liebmann , Allen H. Gabor , Ronald L. Gordon , Carlos A. Fonseca , Martin Burkhardt
IPC分类号： G03F1/00 , G06F17/50 , H01L21/027
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/70125 , G06F17/5068 , G06F2217/12
摘要： A method of designing a mask for imaging an integrated circuit (IC) design layout is provided to efficiently configure subresolution assist features (SRAFs) corresponding to an optimally configured annular illumination source of a lithographic projection system. A critical pitch is identified for the IC design, and optimal inner and outer radial coordinates of an annular illumination source are determined so that the resulting image projected through the mask will be optimized for the full range of pitches in the design layout. A relationship is provided for determining an optimal inner radius and outer radius for the annular illumination source. The number and placement of SRAFs are added to the mask design so that the resulting range of pitches substantially correspond to the critical pitch. The method of configuring SRAFs so that the image will have optimal characteristics, such as good contrast and good depth of focus, is fast.
摘要翻译：提供了一种设计用于对集成电路（IC）设计布局进行成像的掩模的方法，以有效地配置对应于光刻投影系统的最佳配置的环形照明源的分解辅助特征（SRAF）。确定IC设计的关键音调，并且确定环形照明光源的最佳内外径向坐标，以便通过掩模投射的所得图像将针对设计布局中的全部音高进行优化。提供了用于确定环形照明源的最佳内半径和外半径的关系。将SRAF的数量和位置添加到掩模设计中，使得所得到的间距范围基本上对应于临界间距。配置SRAF的方法是使图像具有最佳特征，如良好的对比度和良好的聚焦深度。

9. 发明授权

US06578190B2 Process window based optical proximity correction of lithographic images 有权
公开(公告)号：US06578190B2
公开(公告)日：2003-06-10
申请号：US09759013
申请日：2001-01-11
申请人： Richard A. Ferguson , Mark A. Lavin , Lars W. Liebmann , Alfred K. Wong
发明人： Richard A. Ferguson , Mark A. Lavin , Lars W. Liebmann , Alfred K. Wong
IPC分类号： G06F1750
CPC分类号： G03F1/70 , G03F1/36
摘要： A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

10. 发明授权

US06338922B1 Optimized alternating phase shifted mask design 失效
标题翻译：优化交替相移掩模设计
公开(公告)号：US06338922B1
公开(公告)日：2002-01-15
申请号：US09566885
申请日：2000-05-08
申请人： Lars W. Liebmann , Alfred K. Wong
发明人： Lars W. Liebmann , Alfred K. Wong
IPC分类号： G03F900
CPC分类号： G03F7/70425 , G03F1/30
摘要： A method for reducing lens aberrations sensitivity and proximity effects of alternating phase shifted masks is described. The critical features of a chip design layout are first identified. Multiple, narrow phase regions and auxiliary phase transitions, which provide additional opaque features, are then formed alongside the critical features such that a grating pattern of substantially uniform pitch is printed. Together with a complementary trim mask, the circuit pattern so delineated has reduced sensitivity to lens aberrations and proximity effects.
摘要翻译：描述了用于减少交替相移掩模的透镜像差灵敏度和邻近效应的方法。首先确定了芯片设计布局的关键特征。然后，在临界特征旁边形成提供附加的不透明特征的多个窄相位区域和辅助相位转变，使得印刷基本均匀的间距的光栅图案。与互补的修剪掩模一起，如此描绘的电路图案降低了对透镜像差和邻近效应的敏感性。

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