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1. 发明申请

US20060001058A1 Fin field effect transistor memory cell 审中-公开
标题翻译： Fin场效应晶体管存储单元
公开(公告)号：US20060001058A1
公开(公告)日：2006-01-05
申请号：US11157496
申请日：2005-06-20
申请人： Lars Dreeskornfeld , Jessica Hartwich , Franz Hofmann , Johannes Kretz , Michael Specht
发明人： Lars Dreeskornfeld , Jessica Hartwich , Franz Hofmann , Johannes Kretz , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/42384 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/66795 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region, and a word line region on at least one part of the charge storage layer. The charge storage layer is set up such that electrical charge carriers can be selectively introduced into the charge storage layer or be removed therefrom by applying predetermined electrical potentials to the fin field effect transistor memory cell.
摘要翻译：具有第一和第二源极/漏极区域的栅极场效应晶体管存储单元，栅极区域，具有在第一和第二源极/漏极区域之间的沟道区域的半导体鳍片，被配置为俘获层的电荷存储层，至少部分地在栅极区域上，以及电荷存储层的至少一部分上的字线区域。电荷存储层被设置成使得电荷载流子可以选择性地引入电荷存储层中，或者通过向鳍式场效应晶体管存储单元施加预定的电位而将其移除。

2. 发明申请

US20060181925A1 Nonvolatile memory cell arrangement 有权
标题翻译：非易失性存储单元布置
公开(公告)号：US20060181925A1
公开(公告)日：2006-08-17
申请号：US11283572
申请日：2005-11-18
申请人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
发明人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.
摘要翻译：存储晶体管被布置成多个行和列。第一列的每个存储晶体管的第一源极/漏极端子连接到第一金属化平面中的导电导体轨道，并且与第一列相邻的第二列的每个存储晶体管的第一源极/漏极端子被连接到第二金属化平面中的导电导体轨道。

3. 发明授权

US07411822B2 Nonvolatile memory cell arrangement 有权
标题翻译：非易失性存储单元布置
公开(公告)号：US07411822B2
公开(公告)日：2008-08-12
申请号：US11283572
申请日：2005-11-18
申请人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
发明人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
IPC分类号： G11C11/34 , G11C5/06 , H01L27/10 , H01L29/76 , H01L29/40
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.
摘要翻译：存储晶体管被布置成多个行和列。第一列的每个存储晶体管的第一源极/漏极端子连接到第一金属化平面中的导电导体轨道，并且与第一列相邻的第二列的每个存储晶体管的第一源极/漏极端子被连接到第二金属化平面中的导电导体轨道。

4. 发明授权

US07692246B2 Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement 有权
标题翻译： FinFET晶体管布置的制造方法和相应的FinFET晶体管布置
公开(公告)号：US07692246B2
公开(公告)日：2010-04-06
申请号：US11649470
申请日：2007-01-04
申请人： Lars Dreeskornfeld , Franz Hofmann , Johannes Richard Luyken , Michael Specht
发明人： Lars Dreeskornfeld , Franz Hofmann , Johannes Richard Luyken , Michael Specht
IPC分类号： H01L27/01
CPC分类号： H01L21/823412 , H01L21/823437 , H01L29/66818 , H01L29/7851
摘要： The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b′; 113b″). Formation of the fin-like channel region (113b′; 113b″) has the following steps: forming a hard mask (S1-S4) on the active region (1); anisotropic etching of the active region (1) using the hard mask (S1-S4) forming STI trenches (G1-G5) having an STI oxide filling (9); polishing-back of the STI oxide filling (9); etching-back of the polished-back STI oxide filling (9); selective removal of components of the hard mask forming a modified hard mask (S1′-S4′); anisotropic etching of the active region (1) using the modified hard mask (S1′-S4′) forming widened STI trenches (G1′-G5′), the fin-like channel regions (113b′; 113b″) of the active region (1) remaining for each individual FinFET transistor.
摘要翻译：本发明提供一种使用以下步骤制造的FinFET晶体管布置：步骤：提供衬底（106,108）; 在所述衬底上形成鳍状沟道区（113b'; 113b“）上的有源区（1）。翅片状通道区域（113b'; 113b“）的形成步骤如下：在有源区域（1）上形成硬掩模（S1-S4）; 使用形成具有STI氧化物填充物（9）的STI沟槽（G1-G5）的硬掩模（S1-S4）对有源区域（1）进行各向异性蚀刻。 STI氧化物填充物（9）的抛光; 抛光后的STI氧化物填充物（9）的回蚀; 选择性地去除形成修改的硬掩模（S1'-S4'）的硬掩模的部件; 使用形成加宽的STI沟槽（G1'-G5'）的修改的硬掩模（S1'-S4'）对有源区（1）进行各向异性蚀刻，有源区的鳍状沟道区（113b'; 113b“）（1）保留每个单独的FinFET晶体管。

5. 发明申请

US20070158756A1 Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement 有权
公开(公告)号：US20070158756A1
公开(公告)日：2007-07-12
申请号：US11649470
申请日：2007-01-04
申请人： Lars Dreeskornfeld , Franz Hofmann , Johannes Luyken , Michael Specht
发明人： Lars Dreeskornfeld , Franz Hofmann , Johannes Luyken , Michael Specht
IPC分类号： H01L29/76
CPC分类号： H01L21/823412 , H01L21/823437 , H01L29/66818 , H01L29/7851
摘要： The present invention provides a production method for a FinFET transistor arrangement, and a corresponding FinFET transistor arrangement. The method comprises the following steps: provision of a substrate (106, 108); formation of an active region (1) on the substrate, said active region having a source region (114), a drain region (116) and an intervening fin-like channel region (113b′; 113b″) for each individual FinFET transistor; formation of a gate dielectric (11) and a gate region (13, 14, 15) over the fin-like channel region (113b′; 113b″) for each individual FinFET transistor; the formation of the fin-like channel region (113b′; 113b″) having the following steps: formation of a hard mask (S1-S4) on the active region (1), said hard mask having a pad oxide layer (30), an overlying pad nitride layer (50) and nitride sidewall spacers (7); anisotropic etching of the active layer (1) using the hard mask (S1-S4) for the formation of STI trenches (G1-G5); filling of the STI trenches (G1-G5) with an STI oxide filling (9); polishing-back of the STI oxide filling (9) as far as the top side of the hard mask (S1-S4); etching-back of the polished-back STI oxide filling (9) as far as a residual height (h′) in the STI trenches (G1-G5); selective removal of the pad nitride layer (50) and the nitride sidewall spacers (7) with respect to the pad oxide layer (30), the etched-back STI oxide filling (9) and the active region (1) for the formation of a modified hard mask (S1′-S4′); anisotropic etching of the active layer (1) using the modified hard mask (S1′-S4′) for the formation of widened STI trenches (G1′-G5′), the fin-like channel regions (113b′; 113b″) of the active region (1) remaining for each individual FinFET transistor.

6. 发明授权

US07265376B2 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US07265376B2
公开(公告)日：2007-09-04
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L35/24 , H01L51/00 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入电绝缘层中的电荷载流子的影响。

7. 发明申请

US20050224888A1 Integrated circuit array 审中-公开
标题翻译：集成电路阵列
公开(公告)号：US20050224888A1
公开(公告)日：2005-10-13
申请号：US11116139
申请日：2005-04-27
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.
摘要翻译：集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层门区域。

8. 发明申请

US20060128088A1 Vertical integrated component, component arrangement and method for production of a vertical integrated component 失效
标题翻译：垂直集成部件，组件布置和垂直集成部件生产方法
公开(公告)号：US20060128088A1
公开(公告)日：2006-06-15
申请号：US10533550
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Luyken , Wolfgang Rosner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Luyken , Wolfgang Rosner , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8238
CPC分类号： H01L29/78642 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
摘要翻译：本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。

9. 发明申请

US20050276093A1 Memory cell, memory cell arrangement, patterning arrangement, and method for fabricating a memory cell 审中-公开
标题翻译：存储单元，存储单元布置，图案化布置以及用于制造存储单元的方法
公开(公告)号：US20050276093A1
公开(公告)日：2005-12-15
申请号：US11119531
申请日：2005-04-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L21/8242 , H01L27/108 , H01L51/00 , H01L51/05 , H01L51/30 , G11C11/24
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/16 , H01L27/10841 , H01L27/10864 , H01L27/10876 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L51/057
摘要： A memory cell having a storage capacitor and a vertical switching transistorm, which has a semiconducting nanostructure which has grown on at least part of the storage capacitor and includes a semiconducting nanotube, a bundle of semiconducting nanotubes, or a semiconducting nanorod.
摘要翻译：具有存储电容器和垂直开关转置管的存储单元，其具有在至少部分存储电容器上生长的半导体纳米结构，并且包括半导体纳米管，半导体纳米管束或半导体纳米棒。

10. 发明授权

US07709827B2 Vertically integrated field-effect transistor having a nanostructure therein 失效
标题翻译：其中具有纳米结构的垂直集成的场效应晶体管
公开(公告)号：US07709827B2
公开(公告)日：2010-05-04
申请号：US10533550
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8238
CPC分类号： H01L29/78642 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
摘要翻译：本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。

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