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1. 发明授权

US07183191B2 Method for fabricating a chip scale package using wafer level processing 有权
标题翻译：使用晶片级处理制造芯片级封装的方法
公开(公告)号：US07183191B2
公开(公告)日：2007-02-27
申请号：US11057921
申请日：2005-02-15
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L21/561 , H01L21/563 , H01L21/78 , H01L23/3114 , H01L23/32 , H01L24/11 , H01L24/28 , H01L24/72 , H01L24/81 , H01L24/83 , H01L24/94 , H01L29/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/13022 , H01L2224/13023 , H01L2224/13116 , H01L2224/16 , H01L2224/274 , H01L2224/29111 , H01L2224/73203 , H01L2224/8121 , H01L2224/8122 , H01L2224/81815 , H01L2224/83851 , H01L2224/94 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/0132 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1579 , H01L2224/13099 , H01L2224/13111 , H01L2924/00014 , H01L2924/00 , H01L2224/11 , H01L2224/05624
摘要： Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.
摘要翻译：形成通过半导体衬底的有源表面的通道，以在限定各个管芯位置的相邻活性表面区域之间提供隔离。衬底上的接合焊盘与中间导电元件一起凸起，之后施加用于封装有源表面的材料，填充沟道并覆盖有源表面集成电路的暴露的外围边缘。然后将密封剂平坦化以暴露凸块的端部。然后在暴露的凸起端部上形成诸如焊球的外部导电元件。将半导体晶片与通道对准地切割以对半导体器件进行分割，密封剂保持集成电路的边缘基本上气密密封。

2. 发明授权

US06780746B2 Method for fabricating a chip scale package using wafer level processing and devices resulting therefrom 失效
标题翻译：使用晶片级处理和由此产生的器件制造芯片级封装的方法
公开(公告)号：US06780746B2
公开(公告)日：2004-08-24
申请号：US09917127
申请日：2001-07-27
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L2144
CPC分类号： H01L24/12 , H01L21/561 , H01L21/563 , H01L21/78 , H01L23/3114 , H01L23/32 , H01L24/11 , H01L24/28 , H01L24/72 , H01L24/81 , H01L24/83 , H01L24/94 , H01L29/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/13022 , H01L2224/13023 , H01L2224/13116 , H01L2224/16 , H01L2224/274 , H01L2224/29111 , H01L2224/73203 , H01L2224/8121 , H01L2224/8122 , H01L2224/81815 , H01L2224/83851 , H01L2224/94 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/0132 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1579 , H01L2224/13099 , H01L2224/13111 , H01L2924/00014 , H01L2924/00 , H01L2224/11 , H01L2224/05624
摘要： Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.
摘要翻译：形成通过半导体衬底的有源表面的通道，以在限定各个管芯位置的相邻活性表面区域之间提供隔离。衬底上的接合焊盘与中间导电元件一起凸起，之后施加用于封装有源表面的材料，填充沟道并覆盖有源表面集成电路的暴露的外围边缘。然后将密封剂平坦化以暴露凸块的端部。然后在暴露的凸起端部上形成诸如焊球的外部导电元件。将半导体晶片与通道对准地切割以对半导体器件进行分割，密封剂保持集成电路的边缘基本上气密密封。

3. 发明授权

US06717245B1 Chip scale packages performed by wafer level processing 有权
标题翻译：通过晶片级处理形成的芯片级封装
公开(公告)号：US06717245B1
公开(公告)日：2004-04-06
申请号：US09586243
申请日：2000-06-02
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L2302
CPC分类号： H01L24/12 , H01L21/561 , H01L21/563 , H01L21/78 , H01L23/3114 , H01L23/32 , H01L24/11 , H01L24/28 , H01L24/72 , H01L24/81 , H01L24/83 , H01L24/94 , H01L29/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/13022 , H01L2224/13023 , H01L2224/13116 , H01L2224/16 , H01L2224/274 , H01L2224/29111 , H01L2224/73203 , H01L2224/8121 , H01L2224/8122 , H01L2224/81815 , H01L2224/83851 , H01L2224/94 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/0132 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1579 , H01L2224/13099 , H01L2224/13111 , H01L2924/00014 , H01L2924/00 , H01L2224/11 , H01L2224/05624
摘要： Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.
摘要翻译：形成通过半导体衬底的有源表面的通道，以在限定各个管芯位置的相邻活性表面区域之间提供隔离。衬底上的接合焊盘与中间导电元件一起凸起，之后施加用于封装有源表面的材料，填充沟道并覆盖有源表面集成电路的暴露的外围边缘。然后将密封剂平坦化以暴露凸块的端部。然后在暴露的凸起端部上形成诸如焊球的外部导电元件。将半导体晶片与通道对准地切割以对半导体器件进行分割，密封剂保持集成电路的边缘基本上气密密封。

4. 发明授权

US06268650B1 Semiconductor device, ball grid array connection system, and method of making 有权
标题翻译：半导体器件，球栅阵列连接系统及制作方法
公开(公告)号：US06268650B1
公开(公告)日：2001-07-31
申请号：US09317957
申请日：1999-05-25
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L2352
CPC分类号： H01L23/3107 , H01L24/48 , H01L2224/32225 , H01L2224/451 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A taped ball grid array (BGA) semiconductor device is provided with a metal stiffening layer between the die and the resin tape material. The metal layer is used as an electrical ground plane to simplify the routing pattern of conductive traces on the tape. The metal layer may also be used to dissipate heat from the die. Wires may be employed to connect the die to the conductive traces and to the metal ground plane. Improved structural, thermal and/or electrical performance may be enhanced without substantially increasing the lateral or vertical dimensions of the device. In addition, the device may be produced according to a tape-based manufacturing process.
摘要翻译：带状球栅阵列（BGA）半导体器件在模具和树脂带材料之间设置有金属加强层。金属层用作电接地平面，以简化磁带上导电迹线的布线图案。金属层也可用于从模具散热。可以使用电线将管芯连接到导电迹线和金属接地平面。可以增强改进的结构，热和/或电性能，而不会显着增加装置的横向或垂直尺寸。此外，可以根据基于带的制造工艺来生产该装置。

5. 发明授权

US07727858B2 Method for fabricating a chip scale package using wafer level processing 有权
标题翻译：使用晶片级处理制造芯片级封装的方法
公开(公告)号：US07727858B2
公开(公告)日：2010-06-01
申请号：US11711420
申请日：2007-02-26
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L21/561 , H01L21/563 , H01L21/78 , H01L23/3114 , H01L23/32 , H01L24/11 , H01L24/28 , H01L24/72 , H01L24/81 , H01L24/83 , H01L24/94 , H01L29/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/13022 , H01L2224/13023 , H01L2224/13116 , H01L2224/16 , H01L2224/274 , H01L2224/29111 , H01L2224/73203 , H01L2224/8121 , H01L2224/8122 , H01L2224/81815 , H01L2224/83851 , H01L2224/94 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/0132 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1579 , H01L2224/13099 , H01L2224/13111 , H01L2924/00014 , H01L2924/00 , H01L2224/11 , H01L2224/05624
摘要： Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.
摘要翻译：形成通过半导体衬底的有源表面的通道，以在限定各个管芯位置的相邻活性表面区域之间提供隔离。衬底上的接合焊盘与中间导电元件一起凸起，之后施加用于封装有源表面的材料，填充沟道并覆盖有源表面集成电路的暴露的外围边缘。然后将密封剂平坦化以暴露凸块的端部。然后在暴露的凸起端上形成诸如焊球的外部导电元件。将半导体晶片与通道对准地切割以对半导体器件进行分割，密封剂保持集成电路的边缘基本上气密密封。

6. 发明授权

US07091622B2 Semiconductor device, ball grid array connection system, and method of making 有权
公开(公告)号：US07091622B2
公开(公告)日：2006-08-15
申请号：US10890184
申请日：2004-07-14
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L29/40
CPC分类号： H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/49109 , H01L2224/73215 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor device is provided with a metal stiffening layer between the die and a multilayer structure comprising at least two insulating layers each having at least one conductor thereon. A top insulating layer of the multilayer structure contains a ball grid array. The metal layer is used as an electrical ground plane to simplify the routing pattern of conductive traces on the insulating material. The metal layer may also be used to dissipate heat from the die. The conductors of the multilayer structure provide additional versatility in wiring the die to the ball grid array.

7. 发明授权

US06900079B2 Method for fabricating a chip scale package using wafer level processing 有权
标题翻译：使用晶片级处理制造芯片级封装的方法
公开(公告)号：US06900079B2
公开(公告)日：2005-05-31
申请号：US10624833
申请日：2003-07-22
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L21/56 , H01L21/60 , H01L29/06 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/12 , H01L21/561 , H01L21/563 , H01L21/78 , H01L23/3114 , H01L23/32 , H01L24/11 , H01L24/28 , H01L24/72 , H01L24/81 , H01L24/83 , H01L24/94 , H01L29/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/13022 , H01L2224/13023 , H01L2224/13116 , H01L2224/16 , H01L2224/274 , H01L2224/29111 , H01L2224/73203 , H01L2224/8121 , H01L2224/8122 , H01L2224/81815 , H01L2224/83851 , H01L2224/94 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/0132 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1579 , H01L2224/13099 , H01L2224/13111 , H01L2924/00014 , H01L2924/00 , H01L2224/11 , H01L2224/05624
摘要： Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.
摘要翻译：形成通过半导体衬底的有源表面的通道，以在限定各个管芯位置的相邻活性表面区域之间提供隔离。衬底上的接合焊盘与中间导电元件一起凸起，之后施加用于封装有源表面的材料，填充沟道并覆盖有源表面集成电路的暴露的外围边缘。然后将密封剂平坦化以暴露凸块的端部。然后在暴露的凸起端部上形成诸如焊球的外部导电元件。将半导体晶片与通道对准地切割以对半导体器件进行分割，密封剂保持集成电路的边缘基本上气密密封。

8. 发明授权

US06773965B2 Semiconductor device, ball grid array connection system, and method of making 有权
标题翻译：半导体器件，球栅阵列连接系统及制作方法
公开(公告)号：US06773965B2
公开(公告)日：2004-08-10
申请号：US10119192
申请日：2002-04-10
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L2144
CPC分类号： H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/49109 , H01L2224/73215 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor device is provided with a metal stiffening layer between the die and a multilayer structure comprising at least two insulating layers each having at least one conductor thereon. A top insulating layer of the multilayer structure contains a ball grid array. The metal layer is used as an electrical ground plane to simplify the routing pattern of conductive traces on the insulating material. The metal layer may also be used to dissipate heat from the die. The conductors of the multilayer structure provide additional versatility in wiring the die to the ball grid array.
摘要翻译：半导体器件在管芯和多层结构之间设置有金属加强层，该多层结构包括至少两个各自在其上具有至少一个导体的绝缘层。多层结构的顶部绝缘层包含球栅阵列。金属层用作电接地平面，以简化绝缘材料上的导电迹线的布线图案。金属层也可用于从模具散热。多层结构的导体提供了将管芯连接到球栅阵列的额外的多功能性。

9. 发明授权

US06372552B1 Semiconductor device, ball grid array connection system, and method of making 有权
标题翻译：半导体器件，球栅阵列连接系统及制作方法
公开(公告)号：US06372552B1
公开(公告)日：2002-04-16
申请号：US09653410
申请日：2000-08-31
申请人： Larry D. Kinsman , Salman Akram
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L2144
CPC分类号： H01L23/3107 , H01L24/48 , H01L2224/32225 , H01L2224/451 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A taped ball grid array (BGA) semiconductor device is provided with a metal stiffening layer between the die and the resin tape material. The metal layer is used as an electrical ground plane to simplify the routing pattern of conductive traces on the tape. The metal layer may also be used to dissipate heat from the die. Wires may be employed to connect the die to the conductive traces and to the metal ground plane. Improved structural, thermal and/or electrical performance may be enhanced without substantially increasing the lateral or vertical dimensions of the device. In addition, the device may be produced according to a tape-based manufacturing process.
摘要翻译：带状球栅阵列（BGA）半导体器件在模具和树脂带材料之间设置有金属加强层。金属层用作电接地平面，以简化磁带上导电迹线的布线图案。金属层也可用于从模具散热。可以使用电线将管芯连接到导电迹线和金属接地平面。可以增强改进的结构，热和/或电性能，而不会显着增加装置的横向或垂直尺寸。此外，可以根据基于带的制造工艺来生产该装置。

10. 发明授权

US07871859B2 Vertical surface mount assembly and methods 有权
标题翻译：垂直表面安装组件及方法
公开(公告)号：US07871859B2
公开(公告)日：2011-01-18
申请号：US10202359
申请日：2002-07-23
申请人： Larry D. Kinsman , Jerry M. Brooks , Warren M. Farnworth , Walter L. Moden , Terry R. Lee
发明人： Larry D. Kinsman , Jerry M. Brooks , Warren M. Farnworth , Walter L. Moden , Terry R. Lee
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H05K3/301 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.
摘要翻译：一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。半导体器件的每个接合焊盘都设置在其单个边缘附近。优选地，半导体器件的至少一部分被暴露。对准装置附接到载体基板。可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。优选地，对准装置将垂直安装的半导体器件封装相对于载体衬底垂直固定。接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。垂直安装的半导体器件封装也可以容易地用户升级。

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