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1. 发明授权

US06272465B1 Monolithic PC audio circuit 失效
标题翻译：单片PC音频电路
公开(公告)号：US06272465B1
公开(公告)日：2001-08-07
申请号：US08934969
申请日：1997-09-22
申请人： Larry D. Hewitt , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Michael Hogan , Alfredo R. Linz , David Norris , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
发明人： Larry D. Hewitt , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Michael Hogan , Alfredo R. Linz , David Norris , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
IPC分类号： G10L500
CPC分类号： H03K23/68 , G06F3/162 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.
摘要翻译：用于在个人计算机中提供增强音频性能的单片集成电路。单片电路包括波形合成器; 全功能立体声编解码电路，包括模数转换和数模转换; 数据压缩，模拟信号的混合和复用; 用于与外部存储器接口的本地存储器控制模块; 一个游戏MIDI口模块; 一个系统总线接口; 以及用于兼容性和电路控制功能的控制模块。

2. 发明授权

US5809466A Audio processing chip with external serial port 失效
标题翻译：音频处理芯片带外部串口
公开(公告)号：US5809466A
公开(公告)日：1998-09-15
申请号：US753719
申请日：1996-11-27
申请人： Larry D. Hewitt , Glen W. Brown , Dale E. Gulick , Michael Hogan , David Norris , Martin P. Soques , David N. Suggs
发明人： Larry D. Hewitt , Glen W. Brown , Dale E. Gulick , Michael Hogan , David Norris , Martin P. Soques , David N. Suggs
IPC分类号： G06F7/02 , H03K23/68 , G10L5/00
CPC分类号： H03K23/68 , G06F7/026
摘要： This invention is for a single monolithic audio processing integrated circuit which includes a synthesizer module, a CODEC module and an external serial data port in the CODEC module for bi-directional serial data communication between the CODEC module and an external serial data device, such as a digital signal processor. A serial data path between the synthesizer module and the CODEC module is also included.
摘要翻译：本发明是用于单个单片音频处理集成电路，其包括CODEC模块中的合成器模块，CODEC模块和外部串行数据端口，用于CODEC模块和外部串行数据设备之间的双向串行数据通信，例如数字信号处理器。还包括合成器模块和CODEC模块之间的串行数据路径。

3. 发明授权

US5668338A Wavetable audio synthesizer with low frequency oscillators for tremolo and vibrato effects 失效
标题翻译：具有低频振荡器的波音音频合成器，用于颤音和颤音效果
公开(公告)号：US5668338A
公开(公告)日：1997-09-16
申请号：US333564
申请日：1994-11-02
申请人： Larry D. Hewitt , David N. Suggs , David Norris
发明人： Larry D. Hewitt , David N. Suggs , David Norris
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , G10H1/02
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A digital wavetable audio synthesizer with an LFO generator is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. The LFO generator assigns two triangular-wave LFOs to each of the 32 possible voices. One LFO is dedicated to vibrato (frequency modulation) effects and the other to tremolo (amplitude modulation) effects. It is possible to ramp the depth of each LFO into and out of a programmable maximum. The parameters for each LFO are stored in local memory. When creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations can be added to the read address to create chorus and flange effects.
摘要翻译：描述了具有LFO发生器的数字波表音频合成器。合成器可以生成多达32个高质量的音频数字信号或声音，包括基于延迟的效果。合成器包括地址发生器，其具有寻址波形数据的几种模式。地址发生器的寻址速率控制合成器输出信号的间距。合成器音量发生器具有多种控制音量的模式，为数据添加了包络，右偏移，左偏移和效果音量。合成器LFO发生器可以添加LFO变化：（i）波形数据寻址速率，用于产生颤音效果; 和（ii）声音的音量，用于产生颤音效果。 LFO发生器为32个可能的声音中的每一个分配两个三角波LFO。一个LFO专用于颤音（调频）效果，另一个用于颤音（振幅调制）效果。可以将每个LFO的深度倾斜到可编程最大值之外。每个LFO的参数存储在本地存储器中。当创建基于延迟的效果时，数据存储在几个效果累加器之一中。然后将此数据写入波表。该数据的波形写入和读取地址之间的差异提供了回声和混响效应的延迟。 LFO变体可以添加到读取地址以创建合唱和法兰效果。

4. 发明授权

US5659466A Monolithic PC audio circuit with enhanced digital wavetable audio synthesizer 失效
公开(公告)号：US5659466A
公开(公告)日：1997-08-19
申请号：US333536
申请日：1994-11-02
申请人： David Norris , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Larry D. Hewitt , Michael Hogan , Alfredo R. Linz , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
发明人： David Norris , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Larry D. Hewitt , Michael Hogan , Alfredo R. Linz , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

5. 发明授权

US5675808A Power control of circuit modules within an integrated circuit 失效
标题翻译：集成电路内电路模块的功率控制
公开(公告)号：US5675808A
公开(公告)日：1997-10-07
申请号：US333537
申请日：1994-11-02
申请人： Dele E. Gulick , Larry D. Hewitt , Michael Hogan , David Norris
发明人： Dele E. Gulick , Larry D. Hewitt , Michael Hogan , David Norris
IPC分类号： G06F7/02 , H03K23/68 , G06F1/32
CPC分类号： H03K23/68 , G06F7/026
摘要： A power control and memory refresh rate management circuit is described. The power control circuit provides circuitry for selectively disabling or enabling modular logic circuit blocks within a VLSI integrated circuit under program control from an external processor, or for suspended circuit operation in general. In low-power modes external memory refresh signal generation circuits are provided with a low-frequency oscillator signal to conserve power.
摘要翻译：描述了功率控制和存储器刷新率管理电路。功率控制电路提供电路，用于在来自外部处理器的程序控制下选择性地禁用或启用VLSI集成电路内的模块化逻辑电路块，或者通常用于暂停电路操作。在低功率模式下，外部存储器刷新信号发生电路具有低频振荡器信号以节省功率。

6. 发明授权

US07983181B1 Technique for negotiating a width of a packet-based communication link 有权
标题翻译：用于协商基于分组的通信链路的宽度的技术
公开(公告)号：US07983181B1
公开(公告)日：2011-07-19
申请号：US11379866
申请日：2006-04-24
申请人： Paul Miranda , Larry D. Hewitt
发明人： Paul Miranda , Larry D. Hewitt
IPC分类号： H04L12/26
CPC分类号： H03M13/09 , H04L1/0061 , H04L25/14
摘要： A technique for negotiating the width of a link between a first device and a second device includes detecting, during initialization, a respective signal on one or more control lines associated with at least a portion of an N-bit link. The N-bit link is configured as a single link having a width of N or multiple sublinks having a width less than N based on a respective value of the respective signal on the one or more control lines.
摘要翻译：用于协商第一设备和第二设备之间的链路的宽度的技术包括在初始化期间检测与N位链路的至少一部分相关联的一个或多个控制线上的相应信号。基于一个或多个控制线上的相应信号的相应值，将N位链路配置为宽度为N的单个链路或宽度小于N的多个子链路。

7. 发明授权

US07146510B1 Use of a signal line to adjust width and/or frequency of a communication link during system operation 有权
标题翻译：在系统运行期间使用信号线来调整通信链路的宽度和/或频率
公开(公告)号：US07146510B1
公开(公告)日：2006-12-05
申请号：US10198637
申请日：2002-07-18
申请人： Frank P. Helms , Derrick R. Meyer , Larry D. Hewitt , Dale E. Gulick , William A. Hughes , Scott E. Swanstrom
发明人： Frank P. Helms , Derrick R. Meyer , Larry D. Hewitt , Dale E. Gulick , William A. Hughes , Scott E. Swanstrom
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/151 , Y02D10/172
摘要： An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.
摘要翻译：集成电路耦合到通信链路和单独的信号线，并且包括指定通信链路宽度和频率的可编程寄存器。通过将通信链路的至少一部分的宽度和/或频率响应于信号线的逻辑值的改变而改变为编程值，集成电路响应于信号线的值的变化，而没有集成电路进入复位状态。宽度和/或频率可以在POST程序期间或在系统操作期间作为功率管理或其他系统功能的一部分而改变，同时保持其操作状态。

8. 发明授权

US06725297B1 Peripheral interface circuit for an I/O node of a computer system 有权
标题翻译：用于计算机系统的I / O节点的外围接口电路
公开(公告)号：US06725297B1
公开(公告)日：2004-04-20
申请号：US10093146
申请日：2002-03-07
申请人： Tahsin Askar , Larry D. Hewitt , Eric G. Chambers
发明人： Tahsin Askar , Larry D. Hewitt , Eric G. Chambers
IPC分类号： G06F1300
CPC分类号： G06F13/128
摘要： A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.
摘要翻译：用于计算机系统的I / O节点的外围接口电路。一种用于计算机系统的输入/输出节点的外围接口电路包括第一缓冲电路，第二缓冲电路和总线接口电路。第一缓冲电路接收分组命令，并且可以包括每个对应于多个虚拟通道的相应虚拟通道的第一多个缓冲器。第二缓冲电路被耦合以从总线接口电路接收分组命令，并且可以包括每个对应于多个虚拟通道中的相应虚拟通道的第二多个缓冲器。总线接口电路可以被配置为将存储在第一缓冲器电路中的选择的分组命令转换成适合于在外围总线上传输的命令。

9. 发明授权

US06697890B1 I/O node for a computer system including an integrated I/O interface 有权
标题翻译：包含集成I / O接口的计算机系统的I / O节点
公开(公告)号：US06697890B1
公开(公告)日：2004-02-24
申请号：US10034878
申请日：2001-12-27
申请人： Dale E. Gulick , Larry D. Hewitt
发明人： Dale E. Gulick , Larry D. Hewitt
IPC分类号： G06F1312
CPC分类号： G06F13/4247 , G06F13/4004
摘要： An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may receive and transmit packet transactions on a second link of the packet bus. The packet tunnel may convey selected packet transactions between the first and second transceiver units. The bridge unit may receive particular packet transactions from the first transceiver may transmit transactions corresponding to the particular packet transactions upon a peripheral bus. The I/O interface unit may receive additional packet transactions from the first transceiver unit and may transmit transactions corresponding to the additional packet transactions upon an I/O link.
摘要翻译：一个包含集成I / O接口的计算机系统的I / O节点。在集成电路上实现的用于计算机系统的输入/输出节点包括第一收发器单元，第二收发器单元，分组隧道，桥接单元和I / O接口单元。第一收发器单元可以在分组总线的第一链路上接收和发送分组事务。第二收发器单元可以在分组总线的第二链路上接收和发送分组事务。分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。桥接单元可以接收来自第一收发器的特定分组事务可以在外围总线上发送与特定分组事务相对应的事务。 I / O接口单元可以从第一收发器单元接收附加分组事务，并且可以在I / O链路上传送与附加分组事务相对应的事务。

10. 发明授权

US06385705B1 Circuit and method for maintaining order of memory access requests initiated by devices in a multiprocessor system 有权
公开(公告)号：US06385705B1
公开(公告)日：2002-05-07
申请号：US09702147
申请日：2000-10-30
申请人： James B. Keller , Dale E. Gulick , Larry D. Hewitt , Geoffrey Strongin
发明人： James B. Keller , Dale E. Gulick , Larry D. Hewitt , Geoffrey Strongin
IPC分类号： G06F1300
CPC分类号： G06F13/1621
摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

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