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1. 发明授权

US06272465B1 Monolithic PC audio circuit 失效
标题翻译：单片PC音频电路
公开(公告)号：US06272465B1
公开(公告)日：2001-08-07
申请号：US08934969
申请日：1997-09-22
申请人： Larry D. Hewitt , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Michael Hogan , Alfredo R. Linz , David Norris , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
发明人： Larry D. Hewitt , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Michael Hogan , Alfredo R. Linz , David Norris , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
IPC分类号： G10L500
CPC分类号： H03K23/68 , G06F3/162 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.
摘要翻译：用于在个人计算机中提供增强音频性能的单片集成电路。单片电路包括波形合成器; 全功能立体声编解码电路，包括模数转换和数模转换; 数据压缩，模拟信号的混合和复用; 用于与外部存储器接口的本地存储器控制模块; 一个游戏MIDI口模块; 一个系统总线接口; 以及用于兼容性和电路控制功能的控制模块。

2. 发明授权

US5659466A Monolithic PC audio circuit with enhanced digital wavetable audio synthesizer 失效
公开(公告)号：US5659466A
公开(公告)日：1997-08-19
申请号：US333536
申请日：1994-11-02
申请人： David Norris , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Larry D. Hewitt , Michael Hogan , Alfredo R. Linz , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
发明人： David Norris , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Larry D. Hewitt , Michael Hogan , Alfredo R. Linz , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

3. 发明授权

US5809466A Audio processing chip with external serial port 失效
标题翻译：音频处理芯片带外部串口
公开(公告)号：US5809466A
公开(公告)日：1998-09-15
申请号：US753719
申请日：1996-11-27
申请人： Larry D. Hewitt , Glen W. Brown , Dale E. Gulick , Michael Hogan , David Norris , Martin P. Soques , David N. Suggs
发明人： Larry D. Hewitt , Glen W. Brown , Dale E. Gulick , Michael Hogan , David Norris , Martin P. Soques , David N. Suggs
IPC分类号： G06F7/02 , H03K23/68 , G10L5/00
CPC分类号： H03K23/68 , G06F7/026
摘要： This invention is for a single monolithic audio processing integrated circuit which includes a synthesizer module, a CODEC module and an external serial data port in the CODEC module for bi-directional serial data communication between the CODEC module and an external serial data device, such as a digital signal processor. A serial data path between the synthesizer module and the CODEC module is also included.
摘要翻译：本发明是用于单个单片音频处理集成电路，其包括CODEC模块中的合成器模块，CODEC模块和外部串行数据端口，用于CODEC模块和外部串行数据设备之间的双向串行数据通信，例如数字信号处理器。还包括合成器模块和CODEC模块之间的串行数据路径。

4. 发明授权

US5648778A Stereo audio CODEC 失效
标题翻译：立体声音频编解码器
公开(公告)号：US5648778A
公开(公告)日：1997-07-15
申请号：US683754
申请日：1996-07-17
申请人： Alfredo R. Linz , Carlin Dru Cabler , Glen W. Brown , Martin P. Soques
发明人： Alfredo R. Linz , Carlin Dru Cabler , Glen W. Brown , Martin P. Soques
IPC分类号： F02B75/02 , G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03M7/32 , H03M1/00
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0058 , G10H1/0066 , G10H1/125 , G10H7/002 , F02B2075/027 , G10H2230/035 , G10H2240/311 , G10H2250/115 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.
摘要翻译：立体声音频CODEC，包括用于执行D / A和A / D转换的装置，用于在衰减/增益变化期间减少数字感应噪声的装置，数据格式转换装置，模拟和数字滤波装置，模拟混合装置，片上16- 采样，32位宽记录和播放FIFO，与外部串行DSP的串行接口，用于补充片上记录和播放FIFO，控制寄存器，寄存器数据总线和合成器DAC的大型本地存储器。

5. 发明授权

US5589830A Stereo audio codec 失效
标题翻译：立体声音频编解码器
公开(公告)号：US5589830A
公开(公告)日：1996-12-31
申请号：US333467
申请日：1994-11-02
申请人： Alfredo R. Linz , Carlin D. Cabler , Glen W. Brown , Martin P. Soques
发明人： Alfredo R. Linz , Carlin D. Cabler , Glen W. Brown , Martin P. Soques
IPC分类号： F02B75/02 , G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03M7/32 , H03M1/00
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0058 , G10H1/0066 , G10H1/125 , G10H7/002 , F02B2075/027 , G10H2230/035 , G10H2240/311 , G10H2250/115 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.
摘要翻译：立体声音频CODEC，包括用于执行D / A和A / D转换的装置，用于在衰减/增益变化期间减少数字感应噪声的装置，数据格式转换装置，模拟和数字滤波装置，模拟混合装置，片上16- 采样，32位宽记录和播放FIFO，与外部串行DSP的串行接口，用于补充片上记录和播放FIFO，控制寄存器，寄存器数据总线和合成器DAC的大型本地存储器。

6. 发明授权

US6029239A Configuring a communications system with a configurable data transfer architecture 失效
标题翻译：配置具有可配置数据传输体系结构的通信系统
公开(公告)号：US6029239A
公开(公告)日：2000-02-22
申请号：US980580
申请日：1997-12-01
申请人： Glen W. Brown
发明人： Glen W. Brown
IPC分类号： G06F9/50 , H04L12/56 , G06F15/00
CPC分类号： H04L49/9089 , G06F9/5016 , H04L12/5693 , H04L47/522 , H04L49/90 , H04L49/901
摘要： A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.
摘要翻译：通信系统利用嵌入式数字信号处理器（DSP），DSP接口和存储架构，微控制器接口，DSP操作系统（OS），数据流模型和硬件块接口。该设计允许软件在使用硬件来提供有效的数据流，信号处理和存储器访问的同时控制架构的大部分配置。在具有嵌入式DSP的器件中，存储器访问通常是瓶颈，并与设计的效率紧密耦合。平台架构涉及允许与其他定制硬件块或微控制器共享DSP存储器的方法。 DSP可以以每百万条指令每秒运行一次（MIPS），而另一个功能则是将数据传输到内存或从内存传输数据。这样可以有效地利用存储器以及在软件和硬件之间分配DSP任务。

7. 发明授权

US06337877B1 Method and apparatus for scaling modem transfer capacity in a multi-channel communications system 有权
标题翻译：用于在多声道通信系统中缩放调制解调器传送容量的方法和装置
公开(公告)号：US06337877B1
公开(公告)日：2002-01-08
申请号：US09141216
申请日：1998-08-27
申请人： Terry L. Cole , Glen W. Brown
发明人： Terry L. Cole , Glen W. Brown
IPC分类号： H04B138
CPC分类号： H04M11/06 , H04L5/0007 , H04L5/0037 , H04L5/0044 , H04L5/1438
摘要： A communications system includes a plurality of lines, a modulator/demodulator, a processing unit, and a negotiation unit. The modulator/demodulator is coupled to the lines and adapted to communicate data over the lines using a plurality of tone sets. Each tone set is associated with a particular line. The processing unit has an amount of available processing resources for supporting the modulator/demodulator and is adapted to generate resource availability data based on the amount of available processing resources. The negotiation unit is adapted to receive the resource availability data from the processing unit and determine a subset of available tones within each tone set based on the resource availability data. The modulator/demodulator is adapted to communicate data on each line using the subset of available tones. A method for allocating the resources of a communications system includes determining an amount of available processing resources for a processing unit. The processing unit is adapted to support a plurality of connections over a plurality of lines. Each connection has an associated tone set for communicating data. A first connection is established over a first line. A first portion of the available processing resources is allocated to the first connection. A first tone range is determined based on the first portion. The first tone range is a subset of the tone set associated with the first line.
摘要翻译：通信系统包括多条线路，调制器/解调器，处理单元和协商单元。调制器/解调器耦合到线路并且适于使用多个音调集合在线路上传送数据。每个音调集合都与特定的行相关联。处理单元具有用于支持调制器/解调器的可用处理资源量，并且适于基于可用处理资源的数量生成资源可用性数据。协商单元适于从处理单元接收资源可用性数据，并且基于资源可用性数据确定每个音调集合内的可用音调的子集。调制器/解调器适于使用可用音调的子集在每条线上传送数据。用于分配通信系统的资源的方法包括确定处理单元的可用处理资源的量。处理单元适于支持多个线路上的多个连接。每个连接具有用于传送数据的相关联的音调集合。在第一行建立第一个连接。可用处理资源的第一部分被分配给第一连接。基于第一部分确定第一音调范围。第一音调范围是与第一行相关联的音调集的子集。

8. 发明授权

US5751615A Implementation of a digital decimation filter and method 失效
标题翻译：数字抽取滤波器和方法的实现
公开(公告)号：US5751615A
公开(公告)日：1998-05-12
申请号：US557511
申请日：1995-11-14
申请人： Glen W. Brown
发明人： Glen W. Brown
IPC分类号： G06F17/10 , H03H17/02 , H03H17/06
CPC分类号： H03H17/0664 , H03H17/0223 , H03H17/0236 , H03H2017/0692
摘要： The present invention is for an implementation of a multi-stage digital decimation filter and a method of decimating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. A compensation stage is also provided. Scaling and multiplication of data with coefficients is performed using a common architecture to the Decim. 2 and Decim. 3 stages. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.
摘要翻译：本发明是为了实现多级数字抽取滤波器以及抽取多比特输入信号的方法，其中执行n / 2次加法，其中n =每个滤波器系数中的比特数。还提供了补偿阶段。数据与系数的缩放和乘法使用Decim的通用架构进行。 2和Decim。 3个阶段具有相关比例因子的系数值被存储在存储器中。系数以编码形式存储，然后在乘以数据值之前被解码。

9. 发明授权

US06128307A Programmable data flow processor for performing data transfers 失效
标题翻译：用于执行数据传输的可编程数据流处理器
公开(公告)号：US06128307A
公开(公告)日：2000-10-03
申请号：US980583
申请日：1997-12-01
申请人： Glen W. Brown
发明人： Glen W. Brown
IPC分类号： G06F9/38 , H04M1/725 , H04M1/73 , H04L12/56
CPC分类号： G06F9/3879 , H04M1/72522
摘要： The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.
摘要翻译：本发明包括涉及嵌入式数字信号处理器（DSP），DSP接口和存储架构，微控制器接口，DSP操作系统（OS），数据流模型和用于硬件块的接口的架构。该设计允许软件在使用硬件来提供有效的数据流，信号处理和存储器访问的同时控制架构的大部分配置。在具有嵌入式DSP的器件中，存储器访问通常是瓶颈，并与设计的效率紧密耦合。平台架构涉及允许与其他定制硬件块或微控制器共享DSP存储器的方法。 DSP可以以每百万条指令每秒运行一次（MIPS），而另一个功能则是将数据传输到内存或从内存传输数据。这样可以有效地利用存储器以及在软件和硬件之间分配DSP任务。

10. 发明授权

US06012136A Communications system with a configurable data transfer architecture 失效
标题翻译：具有可配置数据传输架构的通信系统
公开(公告)号：US06012136A
公开(公告)日：2000-01-04
申请号：US980578
申请日：1997-12-01
申请人： Glen W. Brown
发明人： Glen W. Brown
IPC分类号： H04L12/56 , G06F15/16
CPC分类号： H04L47/522 , H04L12/5693 , H04L47/521 , H04L49/90 , H04L49/9047 , H04L49/9089
摘要： The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.
摘要翻译：本发明包括涉及嵌入式数字信号处理器（DSP），DSP接口和存储架构，微控制器接口，DSP操作系统（OS），数据流模型和用于硬件块的接口的架构。该设计允许软件在使用硬件来提供有效的数据流，信号处理和存储器访问的同时控制架构的大部分配置。在具有嵌入式DSP的器件中，存储器访问通常是瓶颈，并与设计的效率紧密耦合。平台架构涉及允许与其他定制硬件块或微控制器共享DSP存储器的方法。 DSP可以以每百万条指令每秒运行一次（MIPS），而另一个功能则是将数据传输到内存或从内存传输数据。这样可以有效地利用存储器以及在软件和硬件之间分配DSP任务。

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