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1. 发明授权

US6048789A IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids 失效
标题翻译： IC连接形成与化学机械抛光和二氧化硅蚀刻与硝酸和氢氟酸溶液
公开(公告)号：US6048789A
公开(公告)日：2000-04-11
申请号：US807069
申请日：1997-02-27
申请人： Landon B. Vines , Craig A. Bellows , Walter D. Parmantie
发明人： Landon B. Vines , Craig A. Bellows , Walter D. Parmantie
IPC分类号： H01L21/306 , H01L21/3105 , H01L21/311 , H01L21/768 , H01L21/461
CPC分类号： H01L21/7684 , H01L21/02063 , H01L21/31053 , H01L21/31111 , Y10S438/906
摘要： An integrated circuit manufacturing method uses chemical-mechanical polishing (CMP) to planarize a nonplanar submetal (or intermetal) silica dielectric layer. The planarized device is cleaned with an aqueous solution of ammonium hydroxide and citric acid. Exposed hydrated silica is etched using mixture of nitric and hydrofluoric acids, freeing embedded contaminants from the CMP slurry. The hydrofluroic acid is the etching agent, while the nitric acid combines with the freed contaminants to render water soluble products. They are thus carried away in an aqueous rinse, whereas otherwise they might recontaminate the device. A metal interconnect structure is formed on the etched oxide by forming contact apertures, depositing metal, and patterning the metal. The method can be applied also to nonplanar intermetal dielectrics and subsequent metal interconnect layers. The result is an integrated manufacturing method with higher yields and a more reliable manufactured integrated circuit.
摘要翻译：集成电路制造方法使用化学机械抛光（CMP）来平面化非平面亚金属（或金属间）二氧化硅介电层。平面化装置用氢氧化铵和柠檬酸水溶液清洗。使用硝酸和氢氟酸的混合物蚀刻暴露的水合二氧化硅，从CMP浆料中释放嵌入的污染物。氢氟酸是蚀刻剂，而硝酸与被除去的污染物结合以产生水溶性产物。因此，它们在水性漂洗液中携带，否则可能会再次污染该装置。通过形成接触孔，沉积金属和图案化金属，在蚀刻的氧化物上形成金属互连结构。该方法也可以应用于非平面的金属间电介质和随后的金属互连层。结果是具有更高产量和更可靠的制造集成电路的集成制造方法。

2. 发明授权

US5728602A Semiconductor wafer manufacturing process with high-flow-rate low-pressure purge cycles 失效
标题翻译：具有高流量低压吹扫循环的半导体晶圆制造工艺
公开(公告)号：US5728602A
公开(公告)日：1998-03-17
申请号：US657148
申请日：1996-06-03
申请人： Craig A. Bellows , Landon B. Vines
发明人： Craig A. Bellows , Landon B. Vines
IPC分类号： C23C16/40 , C23C16/44 , C23C16/54 , H01L21/302
CPC分类号： C23C16/4408 , C23C16/402 , C23C16/54 , Y10S438/905 , Y10S438/935
摘要： A purge process for an LPCVD TEOS silicon dioxide deposition method uses a series of five purge cycles to allow low-defect wafer processing with less frequent chamber removal and cleaning. The purge process begins by loading dummy wafers into the chamber. Chamber pressure is reduced to below 20 mTorr. A maximal nonreactant gas flow for two minutes is used to dislodge and carry away contaminants such as flakes from silicon dioxide previously deposited on the chamber wall. After the first four of five purge cycles, the method returns to the reduction of chamber pressure, e.g., by maintaining the vacuum on while the gas sources are turned off. After the fifth cycle, the chamber is slowly filled with nitrogen until ambient pressure is reached. Then the dummy wafers are removed. The system is then ready for processing product wafers with reduced particle counts. The purge process is benign in that it only uses equipment and procedures of the type used during product wafer processing. Maintenance involving chamber removal and cleaning is required much less often so that manufacturing throughput is enhanced.
摘要翻译：用于LPCVD TEOS二氧化硅沉积方法的吹扫工艺使用一系列五次清洗循环，以允许低缺陷晶片处理，同时更少的室拆除和清洁。吹扫过程通过将虚拟晶片装入室中开始。室压力降至20 mTorr以下。使用两分钟的最大非反应性气流来移除并携带污染物，例如先前沉积在室壁上的二氧化硅的薄片。在五个吹扫循环的前四个之后，该方法返回到室压力的降低，例如通过在气体源关闭时保持真空。在第五个循环之后，室内缓慢填充氮气直到达到环境压力。然后去除虚拟晶片。然后，该系统准备好处理具有减少的颗粒计数的产品晶片。吹扫过程是良性的，因为它仅使用在产品晶片加工期间使用的类型的设备和程序。需要更少的时间进行维护，以减少制造生产能力。

3. 发明授权

US5745990A Titanium boride and titanium silicide contact barrier formation for integrated circuits 失效
标题翻译：用于集成电路的硼化钛和硅化钛接触屏障形成
公开(公告)号：US5745990A
公开(公告)日：1998-05-05
申请号：US471253
申请日：1995-06-06
申请人： Chang-Ou Lee , Landon B. Vines , Felix H. Fujishiro , Sigmund Koenigseder
发明人： Chang-Ou Lee , Landon B. Vines , Felix H. Fujishiro , Sigmund Koenigseder
IPC分类号： H01L21/285 , H01L21/331 , H01L21/768 , H01K3/10
CPC分类号： H01L21/76864 , H01L21/28518 , H01L21/76841 , H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L29/66272 , Y10T29/49165
摘要： Titanium is deposited using a low-pressure chemical-vapor deposition to provide good step coverage over an underlying integrated circuit structure. A rapid thermal anneal is performed using an ambient including diborane. The rapid thermal anneal causes the titanium to interact with underlying silicon to form titanium silicide. Concurrently, the diborane reacts with the titanium to form titanium boride. A composite barrier layer results. Aluminum is deposited and then patterned together with the composite barrier layer to define a first level metalization. Subsequent intermetal dielectrics, metalization, and passivation layers can be added to form a multi-level metal interconnect structure. The titanium boride prevents the aluminum from migrating into the silicon, while the titanium silicide lowers the contact resistivity associated with the barrier layer. The relatively close match of the thermal coefficients of expansion for titanium boride and silicon provides high thermal stability.
摘要翻译：使用低压化学气相沉积来沉积钛以在下面的集成电路结构上提供良好的阶跃覆盖。使用包括乙硼烷的环境进行快速热退火。快速热退火使钛与下面的硅相互作用形成硅化钛。同时，乙硼烷与钛反应形成硼化钛。产生复合阻挡层。沉积铝，然后与复合阻挡层一起图案化以限定第一级金属化。随后可以加入金属间电介质，金属化和钝化层以形成多层金属互连结构。硼化钛防止铝迁移到硅中，而硅化钛降低与阻挡层相关的接触电阻。硼化钛和硅的热膨胀系数相对较紧密匹配提供了高热稳定性。

4. 发明授权

US5610105A Densification in an intermetal dielectric film 失效
标题翻译：金属间电介质膜中的致密化
公开(公告)号：US5610105A
公开(公告)日：1997-03-11
申请号：US258180
申请日：1994-06-10
申请人： Landon B. Vines , Sigmund A. Koenigseder , John L. Cain , Chang-Ou Lee , Felix Fujishiro
发明人： Landon B. Vines , Sigmund A. Koenigseder , John L. Cain , Chang-Ou Lee , Felix Fujishiro
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/316
CPC分类号： H01L21/76801 , H01L21/3105 , H01L21/76828
摘要： An improved anneal process is disclosed for use in the preparation of a dielectric layer, especially an intermetal dielectric layer. An oxide layer is deposited using a H.sub.2 O-TEOS PECVD process. A vacuum bake is used to minimize or eliminate volatile water, hydrogen, and hydrocarbon impurities in the dielectric layer. An oxidation anneal is then performed to scavenge any remaining undesirable species, and to provide for densification of the dielectric layer.
摘要翻译：公开了一种改进的退火工艺，用于制备电介质层，特别是金属间电介质层。使用H 2 O-TEOS PECVD工艺沉积氧化物层。使用真空烘烤来最小化或消除电介质层中的挥发性水，氢和烃杂质。然后进行氧化退火以清除任何剩余的不期望的物质，并提供电介质层的致密化。

5. 发明授权

US06444502B1 Method for forming strapless anti-fuse structure 失效
标题翻译：形成无肩带反熔丝结构的方法
公开(公告)号：US06444502B1
公开(公告)日：2002-09-03
申请号：US09006926
申请日：1998-01-14
申请人： Ivan Sanchez , Danny Echtle , Landon B. Vines
发明人： Ivan Sanchez , Danny Echtle , Landon B. Vines
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated. The anti-fuse is activated by running a voltage higher than the threshold voltage of the anti-fuse between the interconnect and the plug. Upon activation of the anti-fuse, an electrical connection is made between the interconnect and the metal layer.
摘要翻译：一种用于形成这种结构的抗熔丝结构和方法。在一个实施例中，本发明的抗熔丝结构包括沉积在金属层上的电介质层。然后对半导体衬底进行掩模蚀刻，以在电介质层中形成开口。金属沉积在半导体衬底上并被抛光，以去除覆盖在电介质层上的金属，从而形成延伸穿过电介质层并与金属层电连接的插塞。然后沉积，掩蔽和蚀刻非晶硅块，以在塞上形成非晶硅块。然后沉积，掩蔽和蚀刻金属层以形成互连。非晶硅块位于金属层和互连之间，以防止电流的流动，直到反熔丝被激活为止。通过运行高于互连和插头之间的反熔丝的阈值电压的电压来激活反熔丝。在激活抗熔丝时，在互连和金属层之间形成电连接。

6. 发明授权

US6007641A Integrated-circuit manufacture method with aqueous hydrogen-fluoride and nitric-acid oxide etch 失效
标题翻译：具有氟化氢和硝酸氧化物蚀刻的集成电路制造方法
公开(公告)号：US6007641A
公开(公告)日：1999-12-28
申请号：US818228
申请日：1997-03-14
申请人： Landon B. Vines , Felix H. Fujishiro , Yu-Pin Han
发明人： Landon B. Vines , Felix H. Fujishiro , Yu-Pin Han
IPC分类号： H01L21/28 , H01L21/306 , H01L21/316 , H01L29/51 , B08B3/00
CPC分类号： H01L21/28202 , H01L21/02063 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/02307 , H01L21/31612 , H01L21/31662 , H01L29/518
摘要： In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.
摘要翻译：在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。第二，水性漂洗去除氧化的有机物质和金属污染物。第三，将集成电路浸在氟化氢和硝酸的水溶液中。氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。干燥步骤从集成电路中去除冲洗水。最后，氧化物形成步骤提供相对纯的氧化物层。在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。本发明的主要优点是由于硝酸而改善的钙去除。

7. 发明授权

US5434104A Method of using corrosion prohibiters in aluminum alloy films 失效
标题翻译：在铝合金薄膜中使用腐蚀抑制剂的方法
公开(公告)号：US5434104A
公开(公告)日：1995-07-18
申请号：US204829
申请日：1994-03-02
申请人： John L. Cain , Landon B. Vines , Sigmund Koenigseder , Chang-Ou Lee , Felix Fujishiro
发明人： John L. Cain , Landon B. Vines , Sigmund Koenigseder , Chang-Ou Lee , Felix Fujishiro
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/32051 , H01L21/28512
摘要： A method of metalization of semiconductor devices wherein predominantly aluminum metal films incorporate a minor amount of magnesium in admixture with the aluminum, or in layered juxtaposition with the aluminum layer, to provide resistance to corrosion, particularly acidic corrosion.
摘要翻译：一种半导体器件的金属化方法，其中主要是铝金属膜与铝混合的少量镁，或与铝层分层并置，以提供耐腐蚀性，特别是酸性腐蚀性。

8. 发明授权

US06824448B1 CMP polisher substrate removal control mechanism and method 失效
标题翻译： CMP抛光底物去除控制机理及方法
公开(公告)号：US06824448B1
公开(公告)日：2004-11-30
申请号：US09871507
申请日：2001-05-31
申请人： Landon B. Vines , Parker A. Wood , Paul Douglas, Jr. , Jesse Guzman
发明人： Landon B. Vines , Parker A. Wood , Paul Douglas, Jr. , Jesse Guzman
IPC分类号： B24B100
CPC分类号： B24B53/017
摘要： A slurry removal control mechanism for a CMP polisher is provided. After slurry dispense has been terminated, a high pressure fluid spray removes the slurry from the polishing pad, while the plated causes the pad to rotate at a high rpm rate, thus clearing the slurry from contact with the wafer. Additionally, there is provided a slurry dispense bar including high pressure spray nozzles for providing a high pressure spray upon slurry dispense termination.
摘要翻译：提供了一种用于CMP抛光机的浆料去除控制机构。在浆料分配终止之后，高压流体喷射从抛光垫移除浆料，而镀层使得焊盘以高转速转动，从而使浆料与晶片接触。此外，提供了一种浆料分配棒，其包括用于在浆料分配终止时提供高压喷雾的高压喷嘴。

9. 发明授权

US5493926A Method of identifying a weakest interface where delamination is most likely to occur in a multi-layer dielectric film stack 失效
标题翻译：识别在多层电介质膜叠层中最有可能发生分层的最弱界面的方法
公开(公告)号：US5493926A
公开(公告)日：1996-02-27
申请号：US408652
申请日：1995-03-21
申请人： Landon B. Vines , Felix H. Fujishiro , Danny W. Echtle , Annette Garcia
发明人： Landon B. Vines , Felix H. Fujishiro , Danny W. Echtle , Annette Garcia
IPC分类号： G01N3/46 , G01N19/04 , H01L21/66 , G01N17/00
CPC分类号： G01N19/04 , G01N3/46 , H01L22/12
摘要： A method of identifying a weakest interface where delamination is most likely to occur in a multi-layer dielectric film stack formed on a semiconductor wafer includes scribing processed layers including the multi-layer dielectric film stack with an applied force of a selected and constant magnitude, measuring the depth of a cavity formed in the processed layers by such scribing, and identifying the weakest interface by comparing the measured depth against the known depths of the interfaces between adjacent layers of the multi-layer dielectric film stack.
摘要翻译：识别在形成在半导体晶片上的多层电介质膜堆叠中最有可能发生分层的最弱界面的方法包括使用选定且恒定幅度施加的力划分包括多层电介质膜叠层的处理层，通过这种划线来测量在处理层中形成的腔的深度，并且通过将测量的深度与多层电介质膜叠层的相邻层之间的界面的已知深度进行比较来识别最弱的界面。

10. 发明授权

US06429144B1 Integrated circuit manufacture method with aqueous hydrogen fluoride and nitric acid oxide etch 失效
标题翻译：具有氟化氢水溶液和硝酸氧化物蚀刻的集成电路制造方法
公开(公告)号：US06429144B1
公开(公告)日：2002-08-06
申请号：US09473451
申请日：1999-12-28
申请人： Landon B. Vines , Felix H. Fujishiro , Yu-Pin Han
发明人： Landon B. Vines , Felix H. Fujishiro , Yu-Pin Han
IPC分类号： H01L21302
CPC分类号： H01L21/31111 , H01L21/0206 , H01L21/28211 , H01L21/28238
摘要： In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.
摘要翻译：在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。第二，水性漂洗去除氧化的有机物质和金属污染物。第三，将集成电路浸在氟化氢和硝酸的水溶液中。氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。干燥步骤从集成电路中去除冲洗水。最后，氧化物形成步骤提供相对纯的氧化物层。在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。本发明的主要优点是由于硝酸而改善的钙去除。

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